AD7940BRM-REEL7 Datasheet AD7940BRMZ-REEL7, AD7940BRM-REEL7, AD7940BRJZ-REEL7 | P16-P18

AD7940

Rev. A | Page 15 of 20

POWER VS. THROUGHPUT RATE

By using the power-down mode on the AD7940 when not

converting, the average power consumption of the ADC

decreases at lower throughput rates. Figure 19 shows how as the

throughput rate is reduced, the part remains in its shutdown

state longer, and the average power consumption over time

drops accordingly.

For example, if the AD7940 is operated in a continuous

sampling mode, with a throughput rate of 10 kSPS and an SCLK

of 2.5 MHz (V

= 3.6 V), and the device is placed in power-

down mode between conversions, the power consumption is

calculated as follows. The maximum power dissipation during

normal operation is 6.84 mW (V

= 3.6 V). If the power-up

time from power-down is 1 µs, and the remaining conversion

time is 6.4 µs, (using a 16 SCLK transfer), then the AD7940 can

be said to dissipate 6.84 mW for 7.4 µs during each conversion

cycle. With a throughput rate of 10 kSPS, the cycle time is 100

µs. For the remainder of the conversion cycle, 92.6 µs, the part

remains in power-down mode. The AD7940 can be said to

dissipate 1.08 µW for the remaining 92.6 µs of the conversion

cycle. Therefore, with a throughput rate of 10 kSPS, the average

power dissipated during each cycle is

(7.4/100) × (6.84 mW) + (92.6/100) × (1.08 µW) = 0.51 mW

Figure 19 shows the power dissipation versus the throughput

rate when using the power-down mode with 3.6 V supplies and

a 2.5 MHz SCLK.

03305-0-012

POWER (mW)

0.01

0 5 10 15 20 25

THROUGHPUT (kSPS)

30 35 40 45 50

0.1

= 3.6V

SCLK

= 2.5MHz

Figure 19. Power vs. Throughput Using Power-Down Mode at 3.6 V

AD7940

Rev. A | Page 16 of 20

SERIAL INTERFACE

Figure 20 shows the detailed timing diagram for serial

interfacing to the AD7940. The serial clock provides the

conversion clock and also controls the transfer of information

from the AD7940 during conversion.

The

signal initiates the data transfer and conversion process.

The falling edge of

puts the track-and-hold into hold mode,

takes the bus out of three-state, and samples the analog input.

The conversion is also initiated at this point and will require at

least 16 SCLK cycles to complete. Once 15 SCLK falling edges

have elapsed, the track-and-hold will go back into track mode

on the next SCLK rising edge as shown in

Figure 20 at Point B.

On the 16th SCLK falling edge, the SDATA line will go back

into three-state. If the rising edge of

occurs before 16 SCLKs

have elapsed, the conversion will be terminated and the SDATA

line will go back into three-state; otherwise SDATA returns to

three-state on the 16th SCLK falling edge as shown in Figure 20.

Sixteen serial clock cycles are required to perform the

conversion process and to access data from the AD7940.

going low provides the first leading zero to be read in by the

microcontroller or DSP. The remaining data is then clocked out

by subsequent SCLK falling edges beginning with the second

leading zero, thus the first falling clock edge on the serial clock

has the first leading zero provided and also clocks out the

second leading zero. The data transfer will consist of two

leading zeros followed by the 14 bits of data. The final bit in the

data transfer is valid on the 16th falling edge, having been

clocked out on the previous (15th) falling edge.

It is also possible to take valid data on each SCLK rising edge

rather than falling edge, since the SCLK cycle time is long

enough to ensure the data is ready on the rising edge of SCLK.

However, the first leading zero will still be driven by the

falling edge, and so it can be taken only on the first SCLK

falling edge. It may be ignored, and the first rising edge of SCLK

after the

falling edge would have the second leading zero

provided and the 15th rising SCLK edge would have DB0

provided. This method may not work with most

microcontrollers/DSPs, but could possibly be used with FPGAs

and ASICs.

03305-0-013

CONVERT

2 LEADING ZEROS

3-STATE 3-STATE

SCLK

1 2 3 4 5 13 14 15 16

SDATA

0 ZERO DB13 DB12 DB11 DB10 DB2 DB1 DB0

QUIET

Figure 20. AD7940 Serial Interface Timing Diagram

AD7940

Rev. A | Page 17 of 20

MICROPROCESSOR INTERFACING

The serial interface on the AD7940 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7940 with some of the

more common microcontroller and DSP serial interface

protocols.

AD7940 TO TMS320C541

The serial interface on the TMS320C541 uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices such as the

AD7940. The

input allows easy interfacing between the

TMS320C541 and the AD7940 with no glue logic required. The

serial port of the TMS320C541 is set up to operate in burst

mode with internal CLKX (TX serial clock) and FSX (TX frame

sync). The serial port control register (SPC) must have the

following setup:

FO = 0

FSM = 1

MCM = 1

TXM = 1

The format bit, FO, must be set to 1 to set the word length to

8 bits, in order to implement the power-down mode on the

AD7940. The connection diagram is shown in Figure 21. It

should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

TMS320C541 provide equidistant sampling.

03305-0-014

AD7940*

TMS320C541*

*ADDITIONAL PINS OMITTED FOR CLARITY

SDATA DR

FSX

FSR

SCLK

CLKX

CLKR

Figure 21. Interfacing to the TMS320C541

AD7940 TO ADSP-218x

The ADSP-218x family of DSPs can be interfaced directly to the

AD7940 with no glue logic required. The SPORT control regis-

ter should be set up as follows:

TFSW = RFSW = 1, Alternate Framing

INVRFS = INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

SLEN = 1111, 16-Bit Data-Words

ISCLK = 1, Internal Serial Clock

TFSR = RFSR = 0, Frame First Word

IRFS = 0

ITFS = 1

To implement power-down mode, SLEN should be set to 0111

to issue an 8-bit SCLK burst.

The connection diagram is shown in Figure 22. The ADSP-218x

has the TFS and RFS of the SPORT tied together, with TFS set

as an output and RFS set as an input. The DSP operates in

alternate framing mode, and the SPORT control register is set

up as described. The frame synchronization signal generated on

the TFS is tied to

, and, as with all signal processing

applications, equidistant sampling is necessary. In this example,

the timer interrupt is used to control the sampling rate of the

ADC.

03305-0-015

SCLK

AD7940*

SDATA

ADSP-218x*

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

RFS

TFS

Figure 22. Interfacing to the ADSP-218x

The timer register is loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, the values in the transmit autobuffer start to be

transmitted and TFS is generated. The TFS is used to control

the

RFS and, therefore, the reading of data. The data is stored in the

receive autobuffer for processing or to be shifted later. The

frequency of the serial clock is set in the SCLKDIV register.

When the instruction to transmit with TFS is given, i.e., TX0 =

AX0, the state of the SCLK is checked. The DSP waits until the

SCLK has gone high, low, and high before transmission will

start. If the timer and SCLK values are chosen such that the

instruction to transmit occurs on or near the rising edge of

SCLK, the data may be transmitted, or it may wait until the next

clock edge.

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AD7940BRM-REEL7

Mfr. #:

Buy AD7940BRM-REEL7

Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 3mW 100 kSPS 14-Bit

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AD7940BRM-REEL7

AD7940BRM-REEL7

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