MIC2584/2585 Micrel
MIC2584/2585 4 March 2005
Pin Number Pin Number Pin Name Pin Function
MIC2584 MIC2585
3, 14 3, 22 GATE2, GATE1 Gate Drive (Outputs): Connect each output to the gates of external
N-Channel MOSFETs. When ON is asserted, a 14µA current source is
activated and begins to charge the gate of the N-Channel MOSFET connected
to this pin. An internal clamp ensures that no more than 10V is applied
between the GATE and Source when VCC1 or VCC2 is above 5V. When the
circuit breaker trips or when an input undervoltage lockout condition is
detected, the GATE1 and GATE2 pins are immediately brought low.
9 13 GND Ground: Tie to analog ground.
7 10 CPOR Power-On Reset Timer (Input): A capacitor connected between this pin and
ground sets the start-up delay (t
START
) and the power-on reset interval
(t
POR
). Once the lagging supply rises above its UVLO threshold and ON
asserts, the capacitor connected to CPOR begins to charge. When the
voltage at CPOR crosses 0.3V, the start-up threshold (V
START
), a start cycle
is initiated as the GATE outputs begin to ramp while capacitor C
POR
is
immediately discharged to ground. When the voltage at the lagging FB pin
rises above its threshold (V
FB
), capacitor CPOR begins to charge again.
When the voltage at CPOR rises above the power-on reset delay threshold
(V
POR
) of 1.235V, the timer resets by pulling CPOR to ground and /POR is
deasserted. If C
POR
= 0, then t
START
defaults to 20µs.
8 11 CFILTER Current Limit Response Timer (Input): A capacitor connected to this pin
defines the period of time, t
OCSLOW
, in which an overcurrent event must last
to signal a fault condition and trip the circuit breaker. When an overcurrent
condition occurs, a 2.5µA current source begins to charge this capacitor. If
the voltage at this pin reaches 1.235V, the circuit breaker is tripped, both
GATE pins immediately shut off, and /FAULT is asserted. If C
FILTER
= 0,
then t
OCSLOW
defaults to 20µs.
5, 12 7, 18 FB2, FB1 Power-Good Threshold Input (Undervoltage Detect): FB1 and FB2 are
internally compared to 1.235V and 0.80V references with 25mV of hyster-
esis, respectively. External resistive divider networks may be used to set the
voltage at these pins. If either FB input momentarily goes below its thresh-
old, then /POR is activated for one timing cycle, t
POR
, indicating an output
undervoltage condition. The /POR signal deasserts one timing cycle after the
FB pin exceeds its power-good threshold by 25mV. A 5µs filter on these pins
prevents glitches from inadvertently activating the /POR signal.
10 14 /FAULT Circuit Breaker Fault Status (Output): Active-Low, weak pull-up to VCC1 or
open-drain. Asserted when the circuit breaker is tripped due to an
overcurrent, undervoltage lockout, or overvoltage event. When deasserted,
the MIC2585 will initiate a new start cycle by toggling the ON pin.
11 15 /POR Power-On Reset (Output): Active Low, weak pull-up to VCC1 or open drain.
This pin remains asserted during start-up until a time period (t
POR
) after the
lagging FB pin threshold (V
FB1
or V
FB2
) is exceeded. The timing capacitor
C
POR
determines t
POR
. When the output voltage monitored at either FB pin
falls below V
FB
, /POR is asserted for a minimum of one timing cycle (t
POR
).
4, 13 5, 20 OUT2, OUT1 Output Voltage Monitor (Inputs): For output tracking, connect these pins to
their respective output to sense the output voltage.
N/A 12 CDLY Output Sequence Delay Timer (Input): This pin is internally clamped to 6V.
A capacitor connected to this pin sets a timer delay, t
DLY
, between V
OUT1
and V
OUT2
as shown in Figure 5. With this pin pulled up to VCC1 through a
resistor, and if C
GATE1
= C
GATE2
, both V
OUT1
and V
OUT2
ramp up and down
with the same dv/dt as depicted in the Tracking Mode diagram while
maintaining a maximum voltage differential between V
OUT1
and V
OUT2
.
N/A 9 TRK Discharge Tracking Mode Pin (Input): Tie this pin to OUT1 or OUT2 to
enable tracking during turn-off cycle. Ground this pin to disable tracking
during turn-off. The TRK pin is not to be used as a digital input.
