LTC6801
12
6801fc
For more information www.linear.com/LTC6801
OVERVIEW
The LTC6801 is designed as an easy to implement, low-
cost battery stack monitor that provides a simple indica-
tion of correct battery stack operation without requiring
a microcontroller interface. For battery stack monitoring
with cell voltage read back and discharge circuitry, refer
to the LTC6802 battery stack monitor data sheet.
The LTC6801 contains a 12-bit ADC, a precision voltage
reference, sampled comparator, high voltage multiplexer
and timer/sequencer. During normal operation, the se-
quencer multiplexes the ADC inputs between each of the
channel input pins in turn, performing a single comparison
to the undervoltage and overvoltage thresholds. The V
TEMP
inputs are also monitored for an undervoltage at a fixed
threshold of V
REF
/2.
The presence of a status output clock indicates the system
is “OK”. Because the status output is dynamic, it cannot
get stuck in the “OK” state.
STACKED OPERATION
Each LTC6801 monitors a group of up to 12 series con-
nected cells. Groups of cells can be connected in series
or parallel to form a large battery pack. The LTC6801s can
be daisy chained with simple capacitive or transformer
coupling. This allows every cell in a large battery pack
to be monitored with a single signal. Figure 2 illustrates
monitoring of 36 series connected cells.
To cancel systematic duty cycle distortion through the
clock buffers, it is recommended that the clock lines are
cross-coupled (EOUT goes to EIN etc.) as they route up
and down the stack as shown in Figure 2.
APPLICATIONS INFORMATION
INDEPENDENT OPERATION
Figure 3 shows how three groups of 12 cells can be mon-
itored independently.
REGULATED OUTPUTS
A regulated voltage is provided at the V
REG
pin, biased from
the battery stack. The V
REG
pin can supply up to 4mA at
5V and may be used to power small external circuits. The
regulated output remains at 5V continually, as long as the
total stack voltage is between 10V and 50V.
A low current, precision reference voltage is provided at the
V
REF
pin, which can drive loads of greater than 100k. The
V
REF
output is high impedance when the LTC6801 is idle.
Both the V
REG
and V
REF
pins must be bypassed to V
–
with
a 1µF capacitor.
CONTROL INPUTS
The LTC6801 thresholds are controlled by the UV1, UV0,
OV1 and OV0 pins. These pins are designed to be tied
directly to V
REG
, V
REF
or V
–
in order to set the comparison
thresholds for all channels simultaneously. The pins are
not designed to be variable. In particular, changes made
to the pins while the chip is not in idle mode may result
in unpredictable behavior. See Tables 1 and 2 for setting
and threshold information.
