LTC6801
19
6801fc
For more information www.linear.com/LTC6801
APPLICATIONS INFORMATION
In the absence of external noise filtering, the input resis-
tance of the ADC will cause open wires to produce a near
zero reading. This reading will cause an undervoltage
failure during the normal measurement cycle.
Some applications may include external noise filtering to
improve the quality of the voltage comparisons. When
an RC network is used to filter noise, an open wire may
not produce a zero reading because the comparator input
resistance is too large to discharge the capacitors on the
input pin. Charge may build up on the open pin during
successive measurement cycles to the extent that it could
indicate a valid cell voltage reading.
During each self test cycle, the LTC6801 will sink 100µA
to V
–
from each side of the cell being measured. The
undervoltage threshold is not checked during the self test
because the 100µA pull-down current would cause false
failures in some cases. If an input is open, this current will
discharge any filtering capacitors and cause the input to
float down to approximately 0.7V below the next lower cell
input. In most cases, the cell voltage of the cell above the
open input will exceed the overvoltage threshold and flag
a self test error. During the normal measurement cycle,
the LTC6801 will sink 1µA to V
–
from each side of the cell
being measured. If the cell voltages are low enough that
an open wire is not detected as an overvoltage during
self test, this current will cause the cell input to settle to
a voltage low enough to trigger an undervoltage condition
during the normal measurement cycle.
Note, an open cell connection may not be detected when
the UV = 0.766V setting is used. For all other UV settings,
an open cell connection will result in either a self test error
or no SOUT clock.
Using The LTC6801 with Other Battery Monitors
When used in combination with an LTC6802-1, it is possible
to check the LTC6801 self test result via the LTC6802-1 and
its isolated SPI. As shown in Figure 7, the SLTOK output
is tied to the GPIO2 pin on the LTC6802-1. SLTOK will
remain high as long as it is passing the self test. A self test
will occur automatically every
1024 measurement cycles
(17 seconds to 9 minutes, depending on measurement
duty cycle). A self test can be initiated by a falling edge
on S LT , via the LTC6802-1 GPIO1 line. A self test will start
after the current measurement cycle is complete, and the
SLTOK status will be valid when the self test completes.
The worst case delay before SLTOK is valid in continuous
monitor mode is approximately 15ms for the current cycle
to complete plus 17ms for the self test to complete.
The 6802-1 can measure the LTC6801 reference, which
will independently test the analog circuitry of the LTC6802.
Figure 7. Interconnection of an LTC6802-1 and LTC6801 for Self Test.
CSBO
SDOI
SCKO
V
+
C12
S12
C11
S11
C10
S10
C9
S9
C8
S8
C7
S7
C6
S6
C5
S5
C4
S4
C9
C8
C7
C6
C5
C4
C3
C2
CSBI
SDO
SDI
SCKI
V
MODE
GPIO2
GPIO1
WDTB
MMB
TOS
V
REG
V
REF
V
TEMP2
V
TEMP1
NC
V
–
S1
C1
S2
C2
S3
C3
LTC6802-1
6801 F07
V
+
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
V
–
V
TEMP1
V
TEMP2
V
REF
V
REG
C12
C11
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
OV1
OV0
UV1
UV0
HYST
CC1
CC0
SLT
SLTOK
DC
EOUT
EOUT
SIN
SIN
SOUT
SOUT
EIN
EIN
LTC6801
IN
OUT
1µF
1M
1µF
100k
V
REF
CMPD6263
