LTC6801
18
6801fc
For more information www.linear.com/LTC6801
Self Test Pins
The S LT pin is used to initiate a self test. It is configured
as an open collector input/output. The pin should be nor-
mally tied to V
REG
with a resistor greater than or equal to
100k or floated. The pin may be pulled low at any time to
initiate a self test cycle.
The device will automatically initiate a self test if S LT has
not been externally activated for 1024 measurement cycles,
and pull down the S LT pin internally to indicate that it is
in self test mode.
The SLTOK pin is a simple logic output. If the previous self
test failed the output is held low, otherwise the output will
be high. The SLTOK pin is high upon power-up. The SLTOK
output can be connected to a microcontroller through an
isolation path.
The LTC6801 status output will remain active while the
SLTOK pin is low. The LTC6801 will continue to monitor
cells if the self test fails. If the next self test passes, the
SLTOK output returns high.
Reference and Comparator Verification
A secondary internal bandgap voltage reference (REF2)
is included in the LTC6801 to aid in verification of the
reference and comparator. During the self test cycle, the
comparator and main reference are used to measure the
REF2 voltage.
To verify the comparator functionality, the upper and
lower thresholds are first set in a close window around
the expected REF2 voltage and the comparator output is
verified. Then the upper threshold is set below the REF2
voltage and the comparator output is verified again. Lastly,
the lower threshold is set above the REF2 voltage and the
comparator output is verified a third time.
The self test guarantees that V
REF
is within 5% of the
specified nominal value. Also, this test guarantees the
analog portion of the ADC is working.
High Voltage Multiplexer Verification
The most dangerous failure mode of the high voltage
multiplexer would be a stuck bit condition in the address
decoder. Such a fault would cause some channels to be
measured repeatedly while other channels are skipped.
A skipped channel could mean a bad cell reading is not
detectable.
Other multiplexer failures, like the simultaneous
selection of multiple channels, or shorts in the signal path,
would result in an undervoltage or overvoltage condition
on at least one of the channels.
The LTC6801 incorporates circuitry to ensure that
all requested channels are measured during each
measurement cycle and none are skipped. If a channel
is skipped, an error is flagged during the self test cycle.
ADC Decimation Filter Verification
The ADC decimation filter test verifies that the digital cir-
cuits in the ADC are working, i.e. there are no stuck bits
in the ADC output register. During each self test cycle,
the LTC6801 feeds two test waveforms into the ADC. The
internally generated waveforms were designed to generate
complementary zebra patterns (alternating 0’s and 1’s)
at the ADC output. If either of the waveforms generates
an incorrect output value, an error is flagged during the
self test cycle.
Open Cell Connection Detection
The open connection detection algorithm ensures that an
open circuit is not misinterpreted as a valid cell reading.
APPLICATIONS INFORMATION
