LTC6801
8
6801fc
For more information www.linear.com/LTC6801
PIN FUNCTIONS
V
+
(Pin 1): Supply Voltage. Tied to the most positive po-
tential in the battery stack. For example, the same potential
as C12 when measuring a stack of 12 cells, or the same
potential as C7 when measuring a stack of 7 cells.
C12, C11, … C1 (Pin 2 to Pin 13): Cell Voltage Inputs.
Up to 12 cells can be monitored. The lowest potential is
tied to V
–
. The next lowest potential is tied to C1 and so
forth. Due to internal overvoltage protection, each C input
must be tied to a potential equal to or greater than the next
lower numbered C input. See the figures in the Applications
Information section for more details on connecting batteries
to the LTC6801. See Electrical Characteristics table for
voltage range and input bias current requirements.
V
–
(Pin 14): Tied to the most negative cell potential (bottom
of monitored cell stack).
V
TEMP1
, V
TEMP2
(Pin 15, Pin 16): Temperature Sensor
Inputs. The ADC will measure the voltages on V
TEMP1
and V
TEMP2
relative to V
–
. The ADC measurements are
referenced to the V
REF
pin voltage. Therefore a simple
thermistor and resistor combination connected to the V
REF
pin can be used to monitor temperature. These pins have
a fixed undervoltage threshold equal to one half V
REF
. A
filtering capacitor to V
–
is recommended. Temperature
sensor input pins may be tied to V
REF
to disable.
V
REF
(Pin 17): Reference Output, Nominally 3.058V. Re-
quires a 1µF bypass capacitor to V
–
. The V
REF
pin can
drive a 100k resistive load connected to V
–
. V
REF
must
be buffered with an LT6003 amplifier, or similar device to
drive heavier loads. V
REF
becomes high impedance when
the IC is disabled or idle between monitoring events.
V
REG
(Pin 18): Regulator Output, Nominally 5V. Requires
a 1µF bypass capacitor to V
–
. The V
REG
pin is capable of
supplying up to 4mA to an external load and is continually
enabled.
EIN, EIN (Pin 19, Pin 20): Differential Enable Input. A
clock signal greater than 2kHz will enable the LTC6801. For
operation with a single-ended enable signal (up to 10kHz),
drive EIN and connect a 1nF capacitor from EIN to V
–
.
SOUT, SOUT (Pin 21, Pin 22): Differential Status Output.
Swings V
–
to V
REG
. This output will toggle at the same
frequency as EIN/EIN when a valid signal is detected at
SIN/SIN and the battery stack being monitored is within
specified parameters, otherwise SOUT is low and SOUT high
.
SIN, SIN (Pin 23, Pin 24): Differential status input from
the IC above. To indicate that the stack is good, SIN must
be the same frequency and phase as EIN. See applications
circuits for interfacing SIN to the SOUT above.
EOUT, EOUT (Pin 25, Pin 26): A Buffered Version of EIN/
EIN. Swings V
–
to V
REG
. Must be capacitively coupled to
the EIN/EIN inputs of the next higher voltage LTC6801 in a
stack, or looped to SIN/SIN of the same chip (pins 23, 24).
DC (Pin 27): Duty Cycle Three-Level Input. This pin may
be tied to V
REG
, V
REF
or V
–
. The DC pin selects the duty
cycle of the monitoring function and has an internal pull-
up to V
REG
. See Table 3.
SLTOK (Pin 28): Self Test Logic Output. SLTOK is held HIGH
(V
REG
voltage) upon reset or successful completion of a
self test cycle. A LOW output level (V
–
voltage) indicates
the last self test cycle failed.
S LT (Pin 29): Self Test Open Collector Input/Output. S LT
initiates a self test cycle when it is pulled low externally.
When a high to low transition is detected, the next scheduled
measurement cycle will be a self test cycle. S LT indicates a
self test cycle is in progress when pulled low internally. A
self test is automatically initiated after 1024 measurement
cycles. This pin has an internal pull-up to V
REG
.
CC0, CC1 (Pin 30, Pin 31): Cell Count Three-Level Inputs.
These pins may be tied to V
REG
, V
REF
or V
–
. CC1 and CC0
select the number of cells attached to the device and each
pin has an internal pull-up to V
REG
. See Table 5.
HYST (Pin 32): Hysteresis Three-Level Input. This pin may
be tied to V
REG
, V
REF
or V
–
. HYST selects the amount of
hysteresis applied to the undervoltage and overvoltage
threshold settings and has an internal pull-down to V
–
.
See Table 4.
