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IR2132JTRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
Features
• Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
• Gate drive supply range from 10 to 20V
• Undervoltage lockout for all channels
• Over-current shutdown turns off all six drivers
• Independent half-bridge drivers
• Matched propagation delay for all channels
• 2.5V logic compatible
• Outputs out of phase with inputs
• Cross-conduction prevention logic
• Also available LEAD-FREE
3-PHASE BRIDGE DRIVER
V
OFFSET
600V max.
I
O
+/- 200 mA / 420 mA
V
OUT
10 - 20V
t
on/off
(typ.) 675 & 425 ns
Deadtime (typ.) 2.5 µs (IR2130)
0.8 µs (IR2132)
Data Sheet No. PD60019 Rev.P
IR2130/IR2132(J)(S) & (PbF)
Description
The IR2130/IR2132(J)(S) is a high voltage, high speed
power MOSFET and IGBT driver with three indepen-
dent high and low side referenced output channels. Pro-
prietary HVIC technology enables ruggedized
monolithic construction. Logic inputs are compatible with
CMOS or LSTTL outputs, down to 2.5V logic. A
ground-referenced operational amplifier provides
analog feedback of bridge current via an external cur-
rent sense resistor. A current trip function which termi-
nates all six outputs is also derived from this resistor.
An open drain
FAULT
signal indicates if an over-cur-
rent or undervoltage shutdown has occurred. The output drivers feature a high pulse current buffer stage designed
for minimum driver cross-conduction. Propagation delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration
which operate up to 600 volts.
www.irf.com 1
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer
to our Application Notes and DesignTips for proper circuit board layout.
Typical Connection
Product Summary
Packages
28-Lead PDIP
28-Lead SOIC
44-Lead PLCC w/o 12 Leads
IR2130/IR2132(J)(S) & (PbF)
2 www.irf.com
Symbol Definition Min. Max. Units
V
B1,2,3
High Side Floating Supply Voltage -0.3 625
V
S1,2,3
High Side Floating Offset Voltage V
B1,2,3
- 25 V
B1,2,3
+ 0.3
V
HO1,2,3
High Side Floating Output Voltage V
S1,2,3
- 0.3 V
B1,2,3
+ 0.3
V
CC
Low Side and Logic Fixed Supply Voltage -0.3 25
V
SS
Logic Ground V
CC
- 25 V
CC
+ 0.3
V
LO1,2,3
Low Side Output Voltage -0.3 V
CC
+ 0.3
V
IN
Logic Input Voltage (
HIN1,2,3
,
LIN1,2,3
& ITRIP) V
SS
- 0.3 (V
SS
+ 15) or
(V
CC
+ 0.3)
whichever is
lower
V
FLT
FAULT
Output Voltage V
SS
- 0.3 V
CC
+ 0.3
V
CAO
Operational Amplifier Output Voltage V
SS
- 0.3 V
CC
+ 0.3
V
CA-
Operational Amplifier Inverting Input Voltage V
SS
- 0.3 V
CC
+ 0.3
dV
S
/dt Allowable Offset Supply Voltage Transient — 50 V/ns
P
D
Package Power Dissipation @ TA ≤ +25°C (28 Lead DIP) — 1.5
(28 Lead SOIC) — 1.6 W
(44 Lead PLCC) — 2.0
Rth
JA
Thermal Resistance, Junction to Ambient (28 Lead DIP) — 83
(28 Lead SOIC) — 78 °C/W
(44 Lead PLCC) — 63
T
J
Junction Temperature — 150
T
S
Storage Temperature -55 150
T
L
Lead Temperature (Soldering, 10 seconds) — 300
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to V
S0
. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.
Note 1: Logic operational for V
S
of (V
S0
- 5V) to (V
S0
+ 600V). Logic state held for V
S
of (V
S0
- 5V) to (V
S0
- V
BS
).
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins, CA- and CAO pins are internally clamped with a 5.2V zener diode.
V
Symbol Definition Min. Max. Units
V
B1,2,3
High Side Floating Supply Voltage V
S1,2,3
+ 10 V
S1,2,3
+ 20
V
S1,2,3
High Side Floating Offset Voltage Note 1 600
V
HO1,2,3
High Side Floating Output Voltage V
S1,2,3
V
B1,2,3
V
CC
Low Side and Logic Fixed Supply Voltage 10 20
V
SS
Logic Ground -5 5
V
LO1,2,3
Low Side Output Voltage 0 V
CC
V
IN
Logic Input Voltage (
HIN1,2,3
,
LIN1,2,3
& ITRIP) V
SS
V
SS
+ 5
V
FLT
FAULT
Output Voltage V
SS
V
CC
V
CAO
Operational Amplifier Output Voltage V
SS
V
SS
+ 5
V
CA-
Operational Amplifier Inverting Input Voltage V
SS
V
SS
+ 5
T
A
Ambient Temperature -40 125 °C
V
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to V
S0
. The V
S
offset rating is tested
with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.
°C
IR2130/IR2132(J)(S) & (PbF)
www.irf.com 3
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
V
IH
Logic “0” Input Voltage (OUT = LO) 21 2.2 — —
V
IL
Logic “1” Input Voltage (OUT = HI) 22 — — 0.8
V
IT,TH+
ITRIP Input Positive Going Threshold 23 400 490 580
V
OH
High Level Output Voltage, V
BIAS
- VO 24 — — 100 V
IN
= 0V, I
O
= 0A
V
OL
Low Level Output Voltage, VO 25 — — 100 V
IN
= 5V, I
O
= 0A
I
LK
Offset Supply Leakage Current 26 — — 50 V
B
= V
S
= 600V
I
QBS
Quiescent V
BS
Supply Current 27 — 15 30 V
IN
= 0V or 5V
I
QCC
Quiescent V
CC
Supply Current 28 — 3.0 4.0 mA V
IN
= 0V or 5V
I
IN+
Logic “1” Input Bias Current (OUT = HI) 29 — 450 650 V
IN
= 0V
I
IN-
Logic “0” Input Bias Current (OUT = LO) 30 — 225 400 V
IN
= 5V
I
ITRIP+
“High” ITRIP Bias Current 31 — 75 150 ITRIP = 5V
I
ITRIP-
“Low” ITRIP Bias Current 32 — — 100 nA ITRIP = 0V
V
BSUV+
V
BS
Supply Undervoltage Positive Going 33 7.5 8.35 9.2
Threshold
V
BSUV-
V
BS
Supply Undervoltage Negative Going 34 7.1 7.95 8.8
Threshold
V
CCUV+
V
CC
Supply Undervoltage Positive Going 35 8.3 9.0 9.7
Threshold
V
CCUV-
V
CC
Supply Undervoltage Negative Going 36 8.0 8.7 9.4
Threshold
R
on,FLT
FAULT
Low On-Resistance 37 — 55 75 Ω
Symbol Definition Figure Min. Typ. Max. Units Test Conditions
t
on
Turn-On Propagation Delay 11 500 675 850
t
off
Turn-Off Propagation Delay 12 300 425 550 V
IN
= 0 & 5V
t
r
Turn-On Rise Time 13 — 80 125 V
S1,2,3
= 0 to 600V
t
f
Turn-Off Fall Time 14 — 35 55
t
itrip
ITRIP to Output Shutdown Prop. Delay 15 400 660 920 V
IN
, V
ITRIP
= 0 & 5V
t
bl
ITRIP Blanking Time — — 400 — V
ITRIP
= 1V
t
flt
ITRIP to FAULT Indication Delay 16 335 590 845 V
IN
, V
ITRIP
= 0 & 5V
t
flt,in
Input Filter Time (All Six Inputs) — — 310 — V
IN
= 0 & 5V
t
fltclr
LIN1,2,3
to FAULT Clear Time 17 6.0 9.0 12.0 V
IN
, V
ITRIP
= 0 & 5V
DT Deadtime (IR2130) 18 1.3 2.5 3.7
(IR2132) 18 0.4 0.8 1.2
SR+ Operational Amplifier Slew Rate (+) 19 4.4 6.2 —
SR- Operational Amplifier Slew Rate (-) 20 2.4 3.2 —
Dynamic Electrical Characteristics
V
BIAS
(V
CC
, V
BS1,2,3
) = 15V, V
S0,1,2,3
= V
SS
, C
L
= 1000 pF and T
A
= 25°C unless otherwise specified. The dynamic
electrical characteristics are defined in Figures 3 through 5.
Static Electrical Characteristics
V
BIAS
(V
CC
, V
BS1,2,3
) = 15V, V
S0,1,2,3
= V
SS
and T
A
= 25°C unless otherwise specified. The V
IN
, V
TH
and I
IN
parameters
are referenced to V
SS
and are applicable to all six logic input leads:
HIN1,2,3
&
LIN1,2,3
. The V
O
and I
O
parameters
are referenced to V
S0,1,2,3
and are applicable to the respective output leads: HO1,2,3 or LO1,2,3.
V
V/µs
µs
ns
V
mV
µA
µA
V
IN
= 0 & 5V
NOTE: For high side PWM, HIN pulse width must be ≥ 1.5µsec
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

IR2132JTRPBF

Mfr. #:
Buy IR2132JTRPBF
Manufacturer:
Infineon Technologies
Description:
Gate Drivers 3 PHASE DRVR INVERTING INPUT
Lifecycle:
New from this manufacturer.
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