NJU8721V-TE1 Datasheet NJU8721V-TE1 | P1-P3

NJU8721

-1-

Ver.2003-08-28

CLASS D HEADPHONE AMPLIFIER FOR DIGITAL AUDIO

! GENERAL DESCRIPTION

The NJU8721 is a class D Headphone Amplifier

featuring 6

th

∆Σ modulation. It includes Digital

Attenuator, Mute, and De-emphasis circuits. It

converts digital source input to PWM signal output

which is converted to analog signal with simple

external LC low-pass filter. The NJU8721 realizes

very high power-efficiency by class D operation.

Therefore, it is suitable for portable audio set and

others.

! FEATURES

# Stereo Headphone Power Amplifier

: 50mW+50mW

# Sixth-order 32f

S

Over Sampling ∆Σ & PWM

# Internal 8f

S

Over Sampling Digital Filter

# Sampling Frequency : 96kHz (Max.)

# De-Emphasis : 32kHz, 44.1kHz, 48kHz

# System Clock : 256f

S

# Digital Processing : Attenuator 107step, LOG Curve

: Mute

# Digital Audio Interface : 16bit, 18bit

: I

2

S, LSB Justified, MSB Justified

# Operating Voltage : 2.4 to 3.6V

# Driving Voltage : V

DD

to 5.25V

# C-MOS Technology

# Package Outline : SSOP20 / QFN28

! PIN CONFIGURATION

! PACKAGE OUTLINE

NJU8721V

PRELIMINARY

OUT

R

V

DDL

STBY

TEST

V

SSR

V

DDR

OUT

L

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

V

SSL

MODE

RST V

SS

MCK

BCK

LRCK

DIN

MUTE

F2/SCK

F1/REQ

F0/DATA

V

DD

QFN28 SSOP20

NJU8721KN1

V

SS

R

OUT

R

V

DD

R

NC

V

DDL

OUT

L

V

SSL

NC

MODE

RST

NC

V

SS

MC

K

NC

TEST

STBY

NC

V

DD

F0/DAT

A

NC

F1/REQ

F2/SCK

MUTE

NC

DIN

LRCK

BCK

28

1

NJU8721

- 2 -

Ver.2003-08-28

! BLOCK DIAGRAM

System

Control

MUTE

STB

Y

F0/DAT

A

F2/SC

K

F1/REQ

MODE

RST

32f

S

6

th

∆Σ

&

PWM

BC

K

LRC

K

DIN

Serial

Audio Data

Interface

8f

S

Over Sampling

Digital Filter

MCK

Power On

Reset Circuit

V

DD

V

SS

V

DDL

V

SSL

OUT

L

V

DDR

V

SSR

OUT

R

Synchronization

Circuit

NJU8721

-3-

Ver.2003-08-28

! TERMINAL DESCRIPTION

No.

SSOP20

QFN28

SYMBOL I/O FUNCTION

1 26 STBY I

Standby Control Terminal

Low : Standby ON High : Standby OFF

2 27 TEST I

Manufacturer Testing Terminal

Normally connect to GND.

3 1 V

SSR

−

Rch Power GND, V

SSR

=0V

4 2 OUT

R

O Rch Output Terminal

5 3 V

DDR

−

Rch Power Supply, V

DDR

=V

DD

to 5.0V

6 5 V

DDL

−

Lch Power Supply, V

DDL

=V

DD

to 5.0V

7 6 OUT

L

O Lch Output terminal

8 7 V

SSL

−

Lch Power GND, V

SSL

=0V

9 9 MODE I

Control Mode selection Terminal

Low : Parallel Control Mode High : Serial Control Mode

10 10 RST I

Reset Terminal

Low : Reset ON High : Reset OFF

11 12 V

SS

−

Logic Power GND, V

SS

=0V

12 13 MCK I

Master Clock Input Terminal

256f

S

clock inputs this terminal.

13 15 BCK I

Serial Audio Data Bit Clock Input Terminal

This clock must synchronize with MCK input signal.

14 16 LRCK I

L/R Channel Clock Input Terminal

This clock must synchronize with MCK input signal.

15 17 DIN I Serial Audio Data Input Terminal

16 19 MUTE I

Mute Control Terminal

Low : Mute ON High : Mute OFF

17 20 F2/SCK I

MODE=”Low” : Serial Audio Interface Format Selection Terminal 2

MODE=”High” : Control Register Data Shift Clock Input Terminal

The data is fetched into the control register by rise edge of SCK

signal.

18 21 F1/REQ I

MODE=”Low” : Serial Audio Interface Format Selection Terminal 1

MODE=”High” : Control Register Data Request Input Terminal

19 23 F0/DATA I

MODE=”Low” : Serial Audio Interface Format Selection Terminal 0

MODE=”High” : Control Register Data Input Terminal

20 24 V

DD

−

Logic Power Supply, V

DD

=3.3V

−

4,8,11,

14,18,22,

25,28

NC −

Non connection

! INPUT TERMINAL STRUCTURE

V

DD

V

SS

Input Terminal

Inside Circuit

NJU8721V-TE1

NJU8721V-TE1

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