NJU8721
- 4 -
Ver.2003-08-28
! FUNCTIONAL DESCRIPTION
(1) Signal Output
PWM signals of L channel and R output from OUT
L
and OUT
R
terminals respectively. These signals are
converted to analog signal by external 2nd-order or over LC filter. The output driver power supplied from V
DDL
,
V
DDR
, V
SSL
, and V
SSR
are required high response power supply against voltage fluctuation like as switching
regulator because Output THD is effected by power supply stability.
(2) Master Clock
Master Clock is 256f
S
clock into MCK terminal for the internal circuit operation clock.
(3) Reset
“L” level input over than 3ms to the RST terminal is initialization signal to initialize the internal circuit. This
initialization signal is synchronized with internal clock and executes logical OR with the internal power on reset
signal. This Reset signal initializes the internal function setting registers also. During initialization, output
terminals of OUT
L
and OUT
R
are high-impedance.
(4) 8f
S
Over Sampling Digital Filter
8f
S
Over Sampling Digital Filter interpolates Audio data and decreases aliasing noise.
It realizes Attenuation and De-Emphasis function by serial function control.
(5) 32f
S
6
th
∆Σ & PWM
32f
S
6
th
∆Σ & PWM convert from Audio data of the 8f
S
Over Sampling Digital Filter to the 32f
S
one bit PWM
data.
Audio
Hi-Z : high-impedance
Figure 1. Reset Timing
RST
Output
Status
Hi-Z BPZ Unmute Audio
BPZ : Charge of bipolar zero
1024/fs
about 350ms
over than 3ms
NJU8721
-5-
Ver.2003-08-28
(6) System Control
(6-1) Standby
Standby functions by “L” level input to the STBY terminal. In busy of Standby, conditions of digital audio
format set, attenuation level, de-emphasis, and attenuator operation time are kept and output terminals of
OUT
L
and OUT
R
are high-impedance.
(6-2) Control Mode Set
A control mode as shown below is selected by the MODE terminal.
MODE Control Method Function Terminals
0 Parallel Digital Audio interface Format Set F0, F1, F2
1 Serial Control Register serial data input DATA, REQ, SCK
Parallel : Digital Audio Interface Format is set directly by using F0, F1, and F2 terminals.
Serial : NJU8721 is controlled serial input data by 3-wire serial interface using DATA, REQ, and
SCK terminals
By this setting, the function of F0/DATA, F1/REQ, and F2/SCK are changed.
Refer to (8-5)F0,F1,F2 about function of F0, F1, and F2 terminals.
Refer to (8)Control Register about function of DATA, REQ, and SCK terminals.
(6-3) Mute
Mute functions by “L” signal into the MUTE terminal. In busy of mute, a current attenuation value
becomes - by internal digital attenuator. And MUTE is stopped by “H” signal into the MUTE terminal, the
attenuation value returns from - to previous value.
MUTE Attenuation Level
0
-
1 Set Value
1024/f
S
1024/f
S
- -
Set Value
MUTE
MCK
Attenuation Value
Set Value
Figure 2. Mute Timing
NJU8721
- 6 -
Ver.2003-08-28
(7) Serial Audio Data Interface
(7-1) Input Data Format Selection
The digital audio interface format is selected out of I
2
S, MSB Justified or LSB Justified, and 16 bits or 18
bits data length.
(7-2) Input Timing
Digital audio signal data into DIN terminal is fetched into the internal shift register by BCK signal rising
edge. The fetched data in the shift register are transferred by rising edge or falling edge of LRCK as
shown below:
Data Format Rising Edge Falling Edge
I
2
S Lch Input Register Rch Input Register
MSB Justified Rch Input Register Lch Input Register
LSB Justified Rch Input Register Lch Input Register
BCK and LRCK must be synchronized with MCK.
Figure 3.1. 16 bits I
2
S Data Format
Left Channel
Right Channel
LRC
BC
K
DIN
14
0
1
15 13 14
0
1
15 13
Right Channel
Left Channel
Figure 3.2. 16 bits MSB Justified Data Format
LRC
BC
K
DIN
13
0
1
14
0
1
1415 1315 15
Figure 3.3. 16 bits LSB Justified Data Format
Left Channel
Right Channel
14
0
12
30
15
14
0
1 2
3
15
LRC
BC
K
DIN

NJU8721V-TE1

Mfr. #:
Manufacturer:
NJR (New Japan Radio)
Description:
Audio Amplifiers Class D Hdphne
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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