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1493K-17LF

P1-P3P4-P6P7-P9P10-P12
PRELIMINARY DATASHEET
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS
ICS1493-17
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 1
ICS1493-17 REV A 101005
Description
The ICS1493-17 is a low-power, low-jitter clock
synthesizer designed to replace multiple crystals and
oscillators in portable audio/video systems. The device
generates a 37 MHz processor clock, a 48 MHz USB
clock, a fixed 22.5792 MHz audio clock, a selectable
24.576 MHz or 22.5792 MHz audio clock, and a 27MHz
reference clock for video. Using ICS’ proprietary mix of
analog and digital Phase-Locked Loop (PLL)
technology, the device spreads the frequency spectrum
of the 37 MHz output, reducing the peak amplitude of by
up to 16 dB. An output enable (OE) pin lowers the chip
power consumption while tri-stating all outputs.
Features
• Extremely low operating current (11 mA)
• Packaged in 20-pin QFN (Pb-free)
• Input crystal or clock frequency of 27 MHz
• Output reference frequency of 27 MHz
• Fixed output frequencies of 37 MHz, 48 MHz and
22.5792 MHz
• Selectable output frequency of either 22.5792 MHz
or 24.576 MHz
• Configurable spread spectrum on 37 MHz output
• Operating core voltage of 1.8 V
• Output voltage of 1.8 V or 2.5 V
• Advanced, low-power CMOS process
Block Diagram
X1
X2
PLL1
(Spread)
PLL2
Crystal
Oscillator/
Clock
Buffer
27 MHz
clock or
crystal input
Optional tuning
capacitors
VDD
GND
27M
37M
3
5
PLL3 22/24M
PLL4 22M
SCK
48M
IIC
Control
Logic
SDATA
OE
VDDO
2
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS SYNTHESIZERS
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 2
ICS1493-17 REV A 101005
Pin Assignment Output Enable Table
Note: OE pin has an internal pull-down resistor.
Pin Descriptions
1
GND
20-pin QFN
48M
VDDO
OE
VDD
GND
VDD
37M
VDDO
22/24M
X1
X2
VDD
27M
GND
22M
GND
SCK
SDATA
GND
6
11
16
OE
Clock Output State
0 Normal Operation
1 Hi-Z
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 GND Power Connect to ground.
2 48M Output 48 MHz clock output. High impedance state when OE
=1.
3 VDDO Power Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin
12.
4OE
Input Output Enable pin. See table above. Internal pull-down resistor.
5 VDD Power Connect to +1.8 V.
6 22M Output 22.5792 MHz clock output. Internal pull-down. High impedance state
when OE
=1.
7 GND Power Connect to ground.
8 SCK Input I
2
C bus clock pin. Internal pull-up resistor.
9 SDATA Input I
2
C bus data pin. Internal pull-up resistor.
10 GND Power Connect to ground.
11 22/24M Output Selectable output clock of either 22.5792M or 24.576M. See table.
Internal pull-down. High impedance state. OE
=1.
12 VDDO Power Output voltage level. Connect to +1.8 or 2.5 V. Same voltage as pin 3.
13
37M
Output Spread spectrum 37 MHz clock output. See table. Internal pull-down.
High impedance state when OE
=1.
14 VDD Power Connect to +1.8 V.
15 GND Power Connect to ground.
16 GND Power Connect to ground.
17 27M Output 27 MHz reference clock output. Internal pull-down. High impedance
state when OE
=1.
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS SYNTHESIZERS
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 3
ICS1493-17 REV A 101005
.
External Components
Decoupling Capacitor
As with any high-performance mixed-signal IC, the
ICS1493-17 must be isolated from system power
supply noise to perform optimally.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
I
2
C External Resistor Connection
The SCK and SDATA pins can be connected to any
voltage between 1.71 V and 2.625 V.
Crystal Load Capacitors
No external crystal load capacitors are required. To
save discrete component cost, the ICS1493-17
integrates on-chip capacitance to support a crystal with
CL=10 pF. It is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
should be placed close to the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed away
from the ICS1493-17. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
18 VDD Power Connect to +1.8 V.
19 X2 Output Connect to 27 MHz crystal or float for clock input.
20 X1 Input Crystal connection. Connect to 27 MHz crystal or clock input.
Pin
Number
Pin
Name
Pin
Type
Pin Description
P1-P3P4-P6P7-P9P10-P12

1493K-17LF

Mfr. #:
Buy 1493K-17LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CLOCK SYNTHESIZER PORTABLE SYSTEMS
Lifecycle:
New from this manufacturer.
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