ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS SYNTHESIZERS
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 7
ICS1493-17 REV A 101005
Serial Data Interface
Data Protocol
The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the
controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest
byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write
and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed
byte is encoded in the command code, as described in the following table.
The block write and block read protocol is outlined in the table below, followed by the corresponding byte write and
byte read protocol. The slave receiver address is 11010010 (D2h).
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations,
these bits should be '0000000'.
Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command code — 8 bit
‘00000000’ stands for block operation
11:18 Command code - 8 bit
‘00000000’ stands for block operation
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Byte count — 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address — 7 bits
29:36 Data byte 0 — 8 bits 28 Read = 1
37 Acknowledge from slave 29 Acknowledge from slave
38:45 Data byte 1 — 8 bits 30:37 Byte count from slave — 8 bits
46 Acknowledge from slave 38 Acknowledge from master
.... ............................. 39:46 Data byte from slave — 8 bits
.... Data byte (N-1) — 8 bits 47 Acknowledge from master
.... Acknowledge from slave 48:55 Data byte from slave — 8 bits
.... Data byte N — 8 bits 56 Acknowledge from master
.... Acknowledge from slave .... Data byte N from slave — 8 bits
.... Stop .... Not Acknowledge from master
.... Stop
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS SYNTHESIZERS
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 8
ICS1493-17 REV A 101005
.
Byte 0: Vendor ID, Revision Code
Byte Write Protocol Byte Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address - 7 bits 2:8 Slave address - 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command code — 8 bit
‘10000000’ stands for byte operation,
bits[1:0] of the command code represents
the offset of the byte to be accessed
11:18 Command code — 8 bit
‘10000000’ stands for byte operation, bits[1:0]
of the command code represents the offset of
the byte to be accessed
19 Acknowledge from slave 19 Acknowledge from slave
20:27 Data byte from master— 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address — 7 bits
29 Stop 28 Read = 1
29 Acknowledge from slave
30:37 Data byte from slave — 8 bits
38 Not Acknowledge from master
39 Stop
Bit @Pup Name Description
7 0 Revision Code(MSB) Revision Code
6 0 Revision Code Revision Code
5 0 Revision Code Revision Code
4 1 Revision Code(LSB) Revision Code
3 1 Vendor ID(MSB) Vendor ID
2 1 Vendor ID Vendor ID
1 1 Vendor ID Vendor ID
0 1 Vendor ID(LSB) Vendor ID
ICS1493-17
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS SYNTHESIZERS
IDT™ / ICS™
CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS 9
ICS1493-17 REV A 101005
Byte 1: Control Register
Byte 2: Control Register
Bit @Pup Name Description
7 1 REF REF Output Enable
0 = Disable, Output pulled low, 1 = Enable
6 1 37SS 37SS Output Enable
0 = Disable, Output pulled low, corresponding PLL shut off.
1 = Enable
5 1 48M 48M Output Enable
0 = Disable, Output pulled low, 1 = Enable
4 1 22/24M 22/24M Clock Output Enable
0 = Disable, Output pulled low, 1 = Enable
3 0 22M 22M Output Enable
0 = Disable, Output pulled low and corresponding PLL off,
1 = Enable
2 1 Reserved Reserved
1 1 Reserved Reserved
0 1 22/24M SEL 22/24M Clock Select
1 = 24.576 MHz, 0 = 22.5792 MHz
Bit @Pup Name Description
7 0 Reserved Reserved
6 0 Reserved Reserved
5 0 Reserved Reserved
4 0 Reserved Reserved
3 0 Reserved Reserved
2 0 SS Table Bit 2:0=000: No Spread
Bit 2:0=001: -0.5% Spread
Bit 2:0=010:-1.0% Spread
Bit 2:0=011: No Spread
Bit 2:0=100: -2.0% Spread
Bit 2:0=101: No Spread
Bit 2:0=110: -3.0% Spread
Bit 2:0=111: No Spread
11 SS Table
00 SS Table

1493K-17LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CLOCK SYNTHESIZER PORTABLE SYSTEMS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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