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Application details L6731B
20/24
The compensation network consists in the internal error amplifier, the impedance networks Z
IN
(R3, R4 and C20) and Z
FB
(R5, C18 and C19). The compensation network has to provide a
closed loop transfer function with the highest 0dB crossing frequency to have fastest transient
response (but always lower than fsw/10) and the highest gain in DC conditions to minimize the
load regulation error. A stable control loop has a gain crossing the 0dB axis with -20dB/decade
slope and a phase margin greater than 45°. To locate poles and zeroes of the compensation
networks, the following suggestions may be used:
● Modulator singularity frequencies:
● Compensation network singularity frequencies:
● Compensation network design:
– Put the gain R
5
/R
3
in order to obtain the desired converter bandwidth
– Place
ω
Z1
before the output filter resonance ω
LC
;
– Place
ω
Z2
at the output filter resonance ω
LC
;
– Place
ω
P1
at the output capacitor ESR zero ω
ESR
;
– Place
ω
P2
at one half of the switching frequency;
– Check the loop gain considering the error amplifier open loop gain.
Figure 12. Asymptotic Bode plot of Converter's open loop gain
CoutL
LC
⋅
=
1
ω
CoutESR
ESR
⋅
=
1
ω
(13)
(14)
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⋅
⋅
=
1918
1918
5
1
1
CC
CC
R
P
ω
204
2
1
CR
P
⋅
=
ω
(15)
(16)
195
1
1
CR
Z
⋅
=
ω
()
4320
2
1
RRC
Z
+⋅
=
ω
(17) (18)
LCC
Vosc
Vin
R
R
ϖϖ
⋅
∆
⋅=
3
5
(19)
