ADG1434YRUZ Datasheet ADG1434YCPZ-REEL7, ADG1434YRUZ, ADG1433YCPZ-REEL7 | P7-P9

Data Sheet ADG1433/ADG1434

Rev. E | Page 7 of 20

ABSOLUTE MAXIMUM RATINGS

T

A

= 25°C, unless otherwise noted.

Table 4.

Parameter Rating

V

DD

to V

SS

35 V

V

DD

to GND −0.3 V to +25 V

V

SS

to GND −25 V to +0.3 V

Analog Inputs

1

V

SS

− 0.3 V to V

DD

+ 0.3 V or

30 mA (whichever occurs first)

Digital Inputs

1

GND − 0.3 V to V

DD

+ 0.3 V or

30 mA (whichever occurs first)

Peak Current, S or D (Pulsed at 1 ms,

10% Duty Cycle Maximum)

250 mA

Continuous Current, S or D

2

Data + 15%

Operating Temperature Range

Industrial (Y Version) −40°C to +125°C

Storage Temperature Range −65°C to +150°C

Junction Temperature 150°C

Reflow Soldering Peak

Temperature (Pb-Free)

260 (+ 0 to −5)°C

1

Overvoltages at A,

EN

, S, or D pins are clamped by internal diodes. Current

must be limited to the maximum ratings given.

2

See data given in the Specifications section (see Table 1 to Table 3).

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Only one absolute maximum rating may be applied at any

one time.

THERMAL RESISTANCE

θ

JA

is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 5.

Package Type θ

JA

θ

JC

Unit

TSSOP 150.4 50 °C/W

LFCSP

30.4

N/A

1

°C/W

1

N/A means not applicable.

ESD CAUTION

ADG1433/ADG1434 Data Sheet

Rev. E | Page 8 of 20

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

S1A

D1

S1B

S2A

D2

S2B

V

DD

IN1

EN

V

SS

S3A

IN2

IN3

D3

S3B

GND

ADG1433

TOP VIEW

(Not to Scale)

06181-003

Figure 4. ADG1433 TSSOP Pin Configuration

06181-005

D1

S1B

S2B

D2

S2A

IN2

IN3

S3A

V

DD

S1A

GND

IN1

V

SS

EN

S3B

D3

NOTES

1. THE EXPOSED PAD IS TIED TO THE

SUBSTRATE, V

SS

.

12

11

10

1

3

4

9

2

6

5

7

8

16

15

14

13

ADG1433

TOP VIEW

(Not to Scale)

Figure 5. ADG1433 LFCSP Pin Configuration

Table 6. ADG1433 Pin Function Descriptions

Pin No.

Mnemonic Description

TSSOP LFCSP

1 15 V

DD

Most Positive Power Supply Potential.

2 16 S1A Source Terminal 1A. Can be an input or an output.

3 1 D1 Drain Terminal 1. Can be an input or an output.

4 2 S1B Source Terminal 1B. Can be an input or an output.

5

3

S2B

Source Terminal 2B. Can be an input or an output.

6

4

D2

Drain Terminal 2. Can be an input or an output.

7 5 S2A Source Terminal 2A. Can be an input or an output.

8 6 IN2 Logic Control Input 2.

9 7 IN3 Logic Control Input 3.

10 8 S3A Source Terminal 3A. Can be an input or an output.

11 9 D3 Drain Terminal 3. Can be an input or an output.

12 10 S3B Source Terminal 3B. Can be an input or an output.

13 11 V

SS

Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.

14 12

EN

Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx

logic inputs determine the on switches.

15 13 IN1 Logic Control Input 1.

16

14

GND

Ground (0 V) Reference.

N/A

1

0 EPAD Exposed Pad. The exposed pad is tied to the substrate, V

SS

.

1 N/A means not applicable.

Table 7. ADG1433 Truth Table

EN

INx SxA SxB

1 X Off Off

0 0 Off On

0 1 On Off

Data Sheet ADG1433/ADG1434

Rev. E | Page 9 of 20

1

2

3

4

5

6

8

20

19

18

17

16

15

13

S1A

D1

S1B

7

S2B

GND

V

SS

IN1

S4A

D4

S4B

14

S3B

9

S2A

12

S3A

10

IN2

11

IN3

D2

D3

NIC

V

DD

IN4

ADG1434

TOP VIEW

(Not to Scale)

NIC = NO INTERNAL CONNECTION.

06181-004

Figure 6. ADG1434 TSSOP Pin Configuration

06181-006

D1

S1B

V

SS

GND

S2B

V

DD

S4B

D4

S3B

D3

D2

S2A

IN2

S3A

IN3

EN

IN1

S1A

IN4

S4A

14

13

12

1

3

4

15

1

2

5

7

6

8

9

10

19

20

18

17

16

ADG1434

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD IS TIED TO THE

SUBSTRATE, V

SS

.

Figure 7. ADG1434 LFCSP Pin Configuration

Table 8. ADG1434 Pin Function Descriptions

Pin No.

Mnemonic Description

TSSOP LFCSP

1 19 IN1 Logic Control Input 1.

2 20 S1A Source Terminal 1A. Can be an input or an output.

3 1 D1 Drain Terminal 1. Can be an input or an output.

4 2 S1B Source Terminal 1B. Can be an input or an output.

5 3 V

SS

Most Negative Power Supply Potential. In single-supply applications, it can be connected to ground.

6 4 GND Ground (0 V) Reference.

7

5

S2B

Source Terminal 2B. Can be an input or an output.

8 6 D2 Drain Terminal 2. Can be an input or an output.

9 7 S2A Source Terminal 2A. Can be an input or an output.

10 8 IN2 Logic Control Input 2.

11 9 IN3 Logic Control Input 3.

12

10

S3A

Source Terminal 3A. Can be an input or an output.

13

11

D3

Drain Terminal 3. Can be an input or an output.

14 12 S3B Source Terminal 3B. Can be an input or an output.

15 N/A

1

NIC No Internal Connection.

16 13 V

DD

Most Positive Power Supply Potential.

17 14 S4B Source Terminal 4B. Can be an input or an output.

18 15 D4 Drain Terminal 4. Can be an input or an output.

19 16 S4A Source Terminal 4A. Can be an input or an output.

20 17 IN4 Logic Control Input 4.

N/A

1

18

EN

Active Low Digital Input. When high, the device is disabled and all switches are off. When low, INx

logic inputs determine the on switches.

N/A

1

0 EPAD Exposed Pad. The exposed pad is tied to the substrate, V

SS

.

1

N/A means not applicable.

Table 9. ADG1434 TSSOP Truth Table

INx SxA SxB

0 Off On

1 On Off

Table 10. ADG1434 LFCSP Truth Table

EN

INx SxA SxB

1 X Off Off

0 0 Off On

0 1 On Off

ADG1434YRUZ

ADG1434YRUZ

Products related to this Datasheet