CY22150KFC Datasheet CY22150KFCT, CY22150KFC | P1-P3

CY22150

One-PLL General-Purpose

Flash-Programmable and 2-Wire Serially

Programmable Clock Generator

Cypress Semiconductor Corporation • 198 Champion Court • San Jose

CA 95134-1709 • 408-943-2600

Document #: 38-07104 Rev. *I Revised January 23, 2009

Features

■

Integrated phase-locked loop (PLL)

■

Commercial and industrial operation

■

Flash programmable

■

Field programmable

■

Two-wire serial programming interface

■

Low skew, low jitter, high accuracy outputs

■

3.3V operation with 2.5V output option

■

16-pin TSSOP

Benefits

■

Internal PLL to generate six outputs up to 200 MHz. Able to

generate custom frequencies from an external crystal or

a driven source.

■

Performance guaranteed for applications that require an

extended temperature range.

■

Nonvolatile reprogrammable technology allows easy customi-

zation, quick turnaround on design changes and product perfor-

mance enhancements, and better inventory control. Parts can

be reprogrammed up to 100 times, reducing inventory of

custom parts and providing an easy method for upgrading

existing designs.

■

The CY22150 can be programmed at the package level.

In-house programming of samples and prototype quantities is

available using the CY3672 FTG Development Kit. Production

quantities are available through Cypress’s value added distri-

bution partners or by using third party programmers from BP

Microsystems‰, HiLo Systems‰, and others.

■

The CY22150 provides an industry standard interface for

volatile, system level customization of unique frequencies and

options. Serial programming and reprogramming allows quick

design changes and product enhancements, eliminates

inventory of old design parts, and simplifies manufacturing.

■

High performance suited for commercial, industrial,

networking, telecom, and other general purpose applications.

■

Application compatibility in standard and low power systems.

■

Industry standard packaging saves on board space.

Part Number Outputs Input Frequency Range Output Frequency Range Specifications

CY22150FC 6 8 MHz to 30 MHz (external crystal)

1 MHz to 133 MHz (driven clock)

80 kHz to 200 MHz (3.3V)

80 KHz to 166.6 MHz (2.5V)

Field programmable

Serially programmable

Commercial temperature

CY22150FI 6 8 MHz to 30 MHz (external crystal)

1 MHz to 133 MHz (driven clock)

80 kHz to 166.6 MHz (3.3V)

80 KHz to 150 MHz (2.5V)

Field programmable

Serially programmable

Industrial temperature

SPI

Control

VDDL

AVDD

VSS

AVSS

SDAT

SCLK

Serial

VSSL

VDD

XIN

XOUT

LCLK1

Divider

PLL

OSC.

LCLK3

VCO

LCLK2

LCKL4

CLK5

CLK6

Bank 1

Divider

Bank 2

Crosspoint

Switch

Programming

Interface

Matrix

Logic Block Diagram

[+] Feedback

CY22150

Document #: 38-07104 Rev. *I Page 2 of 16

Pin Configuration

Figure 1. 16-Pin TSSOP

VSS

VSSL

SCLK

LCLK1

XIN

XOUT

VDD

SDAT

AVSS

LCLK3

LCLK2

CLK6

CLK5

AVDD

VDDL

LCLK4

Table 1. Pin Definitions

Name Number Description

XIN 1 Reference Input. Driven by a crystal (8 MHz to 30 MHz) or external clock (1 MHz to 133 MHz).

Programmable input load capacitors allow for maximum flexibility in selecting a crystal,

regardless of manufacturer, process, performance, or quality

VDD 2 3.3V Voltage Supply

AVDD 3 3.3V Analog Voltage Supply

SDAT 4 Serial Data Input

AVSS 5 Analog Ground

VSSL 6 LCLK Ground

LCLK1 7 Configurable Clock Output 1 at V

DDL

level (3.3V or 2.5V)

LCLK2 8 Configurable Clock Output 2 at V

DDL

level (3.3V or 2.5V)

LCLK3 9 Configurable Clock Output 3 at V

DDL

level (3.3V or 2.5V)

SCLK 10 Serial Clock Output

VDDL 11 LCLK Voltage Supply (2.5V or 3.3V)

LCLK4 12 Configurable Clock Output 4 at V

DDL

level (3.3V or 2.5V)

VSS 13 Ground

CLK5 14 Configurable Clock Output 5 (3.3V)

CLK6 15 Configurable Clock Output 6 (3.3V)

XOUT

[1]

16 Reference Output

Note

1. Float XOUT if XIN is driven by an external clock source.

[+] Feedback

CY22150

Document #: 38-07104 Rev. *I Page 3 of 16

Frequency Calculation and Register Definitions

The CY22150 is an extremely flexible clock generator with four

basic variables that are used to determine the final output

frequency. They are the input reference frequency (REF), the

internally calculated P and Q dividers, and the post divider, which

can be a fixed or calculated value. There are three formulas to

determine the final output frequency of a CY22150 based

design:

■

CLK = ((REF * P)/Q)/Post Divider

■

CLK = REF/Post Divider

■

CLK = REF.

The basic PLL block diagram is shown in Figure 2. Each of the

six clock outputs on the CY22150 has a total of seven output

options available to it. There are six post divider options

available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N

and DIV2N are independently calculated and are applied to

individual output groups. The post divider options can be applied

to the calculated VCO frequency ((REF*P)/Q) or to the REF

directly.

In addition to the six post divider output options, the seventh

option bypasses the PLL and passes the REF directly to the

crosspoint switch matrix.

Figure 2. Basic Block Diagram of CY22150 PLL

(Q+2)

VCO

(2(PB+4)+PO)

LCLK1

LCLK2

LCLK3

LCLK4

CLK5

CLK6

CLKSRC

Crosspoint

Switch Matrix

[44H]

[44H,45H]

[45H]

[45H,46H]

DIV2CLK

REF

PFD

Divider Bank 1

[45H]

DIV1SRC [OCH]

DIV2SRC [47H]

Divider Bank 2

DIV1N [OCH]

DIV2N [47H]

DIV1CLK

/DIV1N

[42H]

[40H], [41H], [42H]

/DIV2N

Qtotal

Ptotal

CLKOE [09H]

[+] Feedback

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

CY22150KFC

Mfr. #:

Buy CY22150KFC

Manufacturer:

Cypress Semiconductor

Description:

IC CLOCK GEN PROG 16-TSSOP

Lifecycle:

New from this manufacturer.

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CY22150KFC

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