Document #: 38-07104 Rev. *I Page 10 of 16
Applications
Controlling Jitter
Jitter is defined in many ways including: phase noise, long term
jitter, cycle to cycle jitter, period jitter, absolute jitter, and deter-
ministic. These jitter terms are usually given in terms of rms,
peak to peak, or in the case of phase noise dBC/Hz with respect
to the fundamental frequency.
Power supply noise and clock output loading are two major
system sources of clock jitter. Power supply noise is mitigated by
proper power supply decoupling (0.1 μF ceramic cap 0.25”) of
the clock and ensuring a low impedance ground to the chip.
Reducing capacitive clock output loading to a minimum lowers
current spikes on the clock edges and thus reduces jitter.
Reducing the total number of active outputs also reduce jitter in
a linear fashion. However, it is better to use two outputs to drive
two loads than one output to drive two loads.
The rate and magnitude that the PLL corrects the VCO frequency
is directly related to jitter performance. If the rate is too slow, then
long term jitter and phase noise is poor. Therefore, to improve
long term jitter and phase noise, reducing Q to a minimum is
advisable. This technique increases the speed of the Phase
Frequency Detector which in turn drive the input voltage of the
VCO. In a similar manner increasing P till the VCO is near its
maximum rated speed also decreases long term jitter and phase
noise. For example: Input Reference of 12 MHz; desired output
frequency of 33.3 MHz. The following solution is possible: Set
Q = 3, P = 25, Post Div = 3. However, the best jitter results is
Q = 2, P = 50, Post Div = 9.
For more information, contact your local Cypress field applica-
tions engineer.
Figure 8. Duty Cycle Definition; DC = t2/t1 Figure 9. Rise and Fall Time Definitions
Figure 10. Peak-to-Peak Jitter
Figure 7. Test Circuit
0.1 mF
V
DD
0.1 mF
AV
DD
CLK out
C
LOAD
GND
OUTPUTS
V
DDL
0.1 μF
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