CAT5172TBI-50GT3

CAT5172
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7
TYPICAL CHARACTERISTICS
Figure 10. Wipers Transition from Position
0xFF to Position 0x00 Relative to the CS
Disable, V
CC
= 5 V
Figure 11. Standby Current
V
CC
(V)
W
CS
65432
100
150
200
250
300
350
400
Figure 12. Gain vs. Bandwidth (Tap 0x80) Figure 13. PSRR
f (KHz) f (KHz)
1000100101
36
30
24
18
12
6
0
1000100101
0
5
10
15
20
25
30
ISB (nA)
A (dB)
PSRR (dB)
T = 45C
T = 25C
T = 90C
V
CC
= 5 V
V
CC
= 3 V
V
CC
= 5 V
V
CC
= 3 V
CAT5172
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8
BASIC OPERATION
The CAT5172 is a 256-position digitally controlled
potentiometer. When power is first applied the wiper
assumes a mid-scale position and will remain there as long
as CS
remians high. Once the power supply is stable the
wiper may be repositioned via the SPI compatible interface.
The rising edge of the CS
signal acts as the transfer
command and each time CS
transitions from LOW to HIGH
the contents of the input register are loaded into the wiper
register.
In the power-up cycle, the input data register is cleared,
setting all bits to 0 and the wiper register is loaded with 0x80
(128 Decimal) which moves the wiper to its midscale
position. If CS
is toggled CAT5172 transfers the contents of
the input data register (0x00) to the wiper register moving
the wiper to the bottom-most position (W = terminal B). This
transfer is independent of whether new data has been input
or not because CS
acts as the transfer command.
PROGRAMMING: VARIABLE RESISTOR
Rheostat Mode
The resistance between terminals A and B, R
AB
, has a
nominal value of 50 kW or 100 kW and has 256 contact
points accessed by the wiper terminal, plus the B terminal
contact. Data in the 8-bit Wiper register is decoded to select
one of these 256 possible settings.
The wipers first connection is at the B terminal,
corresponding to control position 0x00. Ideally this would
present a 0 W between the Wiper and B, but just as with a
mechanical rheostat there is a small amount of contact
resistance to be considered, there is a wiper resistance
comprised of the R
ON
of the FET switch connecting the
wiper output with its respective contact point. In CAT5172
this ‘contact’ resistance is typically 50 W. Thus a connection
setting of 0x00 yields a minimum resistance of 50 W
between terminals W and B.
For a 100 kW device, the second connection, or the first tap
point, corresponds to 441 W (R
WB
= R
AB
/256 + R
W
= 390.6
+ 50 W) for data 0x01. The third connection is the next tap
point, is 831 W (2 390.6 + 50 W) for data 0x02, and so on.
Figure 14 shows a simplified equivalent circuit where the
last resistor string will not be accessed; therefore, there is
1 LSB less of the nominal resistance at full scale in addition
to the wiper resistance.
Figure 14. CAT5172 Equivalent Digital POT Circuit
R
S
Wiper
Register
and
Decoder
A
W
B
R
S
R
S
R
S
The equation for determining the digitally programmed
output resistance between W and B is
R
WB
+
D
256
R
AB
) R
W
(eq. 1)
where D is the decimal equivalent of the binary code loaded
in the 8-bit Wiper register, R
AB
is the end-to-end resistance,
and R
W
is the wiper resistance contributed by the on
resistance of the internal switch.
In summary, if R
AB
= 100 kW and the A terminal is open
circuited, the following output resistance R
WB
will be set for
the indicated Wiper register codes:
Table 7. CODES AND CORRESPONDING R
WB
RESISTANCE FOR R
AB
= 100 kW, V
DD
= 5 V
D (Dec.)
R
WB
(W)
Output State
255 99,559 Full Scale (R
AB
– 1 LSB + R
W
)
128 50,050 Midscale
1 441 1 LSB
0 50 Zero Scale
(Wiper Contact Resistance)
Be aware that in the zero-scale position, the wiper
resistance of 50 W is still present. Current flow between W
and B in this condition should be limited to a maximum
pulsed current of no more than 20 mA. Failure to heed this
restriction can cause degradation or possible destruction of
the internal switch contact.
Similar to the mechanical potentiometer, the resistance of
the digital POT between the wiper W and terminal A also
produces a digitally controlled complementary resistance
R
WA
. When these terminals are used, the B terminal can be
opened. Setting the resistance value for R
WA
starts at a
maximum value of resistance and decreases as the data
loaded in the latch increases in value. The general equation
for this operation is
R
WA
(D) +
256 * D
256
R
AB
) R
W
(eq. 2)
For R
AB
= 100 kW and the B terminal open circuited, the
following output resistance R
WA
will be set for the indicated
Wiper register codes.
CAT5172
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Table 8. CODES AND CORRESPONDING R
WA
RESISTANCE FOR R
AB
= 100 kW, V
DD
= 5 V
D (Dec.)
R
WA
(W)
Output State
255 441 Full Scale
128 50,050 Midscale
1 99,659 1 LSB
0 100,050 Zero Scale
Typical device to device resistance matching is lot
dependent and may vary by up to 20%.
SPI Compatible 3-wire Serial Bus
Control of CAT5172 is through a 3-wire SPI compatible
digital interface (SDI, CS
, and CLK).
The CLK input is rising-edge sensitive and requires crisp
transitions to avoid clocking incorrect data into the serial
input register. When CS
is low, the clock loads data into the
serial register on each positive clock edge (Figure 1). Each
8-bit serial word must be loaded starting with the MSB. The
format of the word is shown in Table 6.
Data loaded into CAT5172’s 8-bit serial input register is
transferred to the internal Wiper register when the CS
line
returns to logic high. Extra MSB bits are ignored.
ESD Protection
GND
LOGIC
Digital
Input
GND
Potentiometer
Figure 15. ESD Protection Networks
Terminal Voltage Operating Range
The CAT5172 V
DD
and GND power supply define the
limits for proper 3-terminal digital potentiometer operation.
Signals or potentials applied to terminals A, B or the wiper
must remain inside the span of V
DD
and GND. Signals
which attempt to go outside these boundaries will be
clamped by the internal forward biased diodes.
W, A, B
CAT5172
LOGIC
GND
Figure 16.
V
DD
Power-up Sequence
Because ESD protection diodes limit the voltage
compliance at terminals A, B, and W (see Figure 15), it is
recommended that V
DD
/GND be powered before applying
any voltage to terminals A, B, and W. The ideal power-up
sequence is: GND, V
DD
, digital inputs, and then V
A/B/W
. The
order of powering V
A
, V
B
, V
W
, and the digital inputs is not
important as long as they are powered after V
DD
/GND.
Power Supply Bypassing
Good design practice employs compact, minimum lead
length layout design. Leads should be as direct as possible.
It is also recommended to bypass the power supplies with
quality low ESR Ceramic chip capacitors of 0.01 mF to
0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic
capacitors can also be applied at the supplies to suppress
transient disturbances and low frequency ripple. As a further
precaution digital ground should be joined remotely to the
analog ground at one point to minimize the ground bounce.
CAT5172
GND
+
10 mF
0.1 mF
Figure 17. Power Supply Bypassing
V
DD
V
DD
C
3
C
1

CAT5172TBI-50GT3

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Digital Potentiometer ICs Linear Single 256 Taps Non Buffer
Lifecycle:
New from this manufacturer.
Delivery:
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