PDF: 09005aef81c7380b/Source: 09005aef81c7380e Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C_128x72.fm - Rev. C 11/07 EN
8 ©2005 Micron Technology, Inc. All rights reserved
1GB (x72, ECC, SR): 184-Pin DDR VLP RDIMM
Electrical Specifications
IDD Specifications
Table 8: I
DD Specifications and Conditions – 1GB
Values are shown for the MT46V128M4 DDR SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
Parameter/Condition Symbol -40B -335 Units
Operating one bank active-precharge current:
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN);
DQ and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
IDD0 2,790 2,340 mA
Operating one bank active-read-precharge current: BL = 2;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
IDD1 3,330 2,880 mA
Precharge power-down standby current: All device banks idle; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
IDD2P 90 90 mA
Idle standby current: CS# = HIGH; All device banks idle;
t
CK =
t
CK (MIN); CKE = HIGH;
Address and other control inputs
changing once per clock cycle; V
IN
=V
REF
for DQ and
DQS
IDD2F 990 810 mA
Active power-down standby current: One device bank active; Power-down mode;
t
CK =
t
CK (MIN); CKE = LOW
I
DD3P 810 630 mA
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
RC =
t
RAS (MAX);
t
CK =
t
CK (MIN); DQ and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per clock cycle
IDD3N 1,080 900 mA
Operating burst READ current: BL = 2; Continuous burst READs; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN);
I
OUT =0mA
I
DD4R 3,420 2,970 mA
Operating burst WRITE current: BL = 2; Continuous burst WRITEs; One device bank
active; Address and control inputs changing once per clock cycle;
t
CK =
t
CK (MIN); DQ
and DQS inputs changing twice per clock cycle
IDD4W 3,510 3,150 mA
Auto refresh current
t
REFC =
t
RFC (MIN) IDD5 6,210 5,220 mA
t
REFC = 7.8125µs IDD5A 198 180 mA
Self refresh current: CKE ≤ 0.2V IDD69090mA
Operating bank interleave READ current: Four device bank interleaving READs
(BL = 4) with auto precharge;
t
RC =
t
RC (MIN);
t
CK =
t
CK (MIN); Address and control
inputs change only during active READ or WRITE commands
I
DD7 8,100 7,290 mA
