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100336
Industrial Version
PLCC DC Electrical Characteristics
(Note 8)
V
EE
= 4.2V to 5.7V, V
CC
= V
CCA
= GND, T
C
= 40°C to +85°C
Note 8: The specified limits represent the worst case value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under worst case conditions.
PLCC AC Electrical Characteristics
V
EE
= 4.2V to 5.7V, V
CC
= V
CCA
= GND
Note 9: The propagation delay specified is for single output switching. Delays may vary up to 250 ps with multiple outputs switching.
Symbol Parameter
T
C
= 40°CT
C
= 0°C to +85°C
Units Conditions
Min Max Min Max
V
OH
Output HIGH Voltage 1085 870 1025 870 mV V
IN
=V
IH (Max)
Loading with
V
OL
Output LOW Voltage 1830 1575 1830 1620 mV or V
IL (Min)
50 to 2.0V
V
OHC
Output HIGH Voltage 1095 1035 mV V
IN
= V
IH(Min)
Loading with
V
OLC
Output LOW Voltage 1565 1610 mV or V
IL (Max)
50 to 2.0V
V
IH
Input HIGH Voltage 1170 870 1165 870 mV Guaranteed HIGH Signal for All Inputs
V
IL
Input LOW Voltage 1830 1480 1830 1475 mV Guaranteed LOW Signal for All Inputs
I
IL
Input LOW Current 0.50 0.50 µAV
IN
= V
IL
(Min)
I
IH
Input HIGH Current 240 240 µAV
IN
= V
IH
(Max)
I
EE
Power Supply Current 165 75 165 80 mA Inputs Open
Symbol Parameter
T
C
= 40°CT
C
= +25°CT
C
= +85°C
Units Conditions
MinMaxMinMaxMinMax
f
SHIFT
Shift Frequency 325 350 350 MHz Figures 2, 3
t
PLH
Propagation Delay
1.00 1.80 1.00 1.80 1.00 1.80 ns
Figures 1, 3
t
PHL
CP to Q
n
, Q
n
(Note 9)
t
PLH
Propagation Delay
2.00 3.30 2.10 3.30 2.10 3.50 ns
Figures 1, 7, 8
t
PHL
CP to TC (Shift) (Note 9)
t
PLH
Propagation Delay
2.40 4.20 2.40 4.20 2.60 4.50 ns
Figures 1, 9
t
PHL
CP to TC (Count) (Note 9)
t
PLH
Propagation Delay
1.40 2.30 1.40 2.30 1.50 2.40 ns
Figures 1, 4
t
PHL
MR to Q
n
, Q
n
(Note 9)
t
PLH
Propagation Delay
2.80 4.90 2.90 5.00 3.10 5.30 ns
Figures 1, 12
t
PHL
MR to TC (Count) (Note 9)
t
PHL
Propagation Delay
2.40 3.80 2.40 3.80 2.50 3.90 ns
Figures 1, 10, 11
MR to TC
(Shift) (Note 9)
t
PLH
Propagation Delay
1.70 2.90 1.80 2.90 1.90 3.10 ns
t
PHL
D
0
/CET to TC Figures 1, 5
t
PLH
Propagation Delay
1.80 3.90 1.90 3.90 2.10 4.20 ns
(Note 9)
t
PHL
S
n
to TC
t
TLH
Transition Time
0.20 1.90 0.35 1.10 0.35 1.10 ns Figures 1, 3
t
THL
20% to 80%, 80% to 20%
t
S
Setup Time
D
3
1.40 0.90 0.90
P
n
1.70 1.40 1.40
ns Figure 6
D
0
/CET 1.80 1.20 1.20
CEP 1.80 1.30 1.30
S
n
3.30 3.30 3.30
MR (Release Time) 2.60 2.50 2.50
t
H
Hold Time
D
3
0.90 0.30 0.30
P
n
1.00 0.20 0.20
ns Figure 6D
0
/CET 0.70 0.20 0.20
CEP 0.60 0.10 0.10
S
n
0.00 0.00 0.00
t
PW
(H) Pulse Width HIGH CP, MR 2.20 2.00 2.00 ns Figures 3, 4
www.fairchildsemi.com 8
100336
Test Circuitry
Notes:
V
CC
, V
CCA
= +2V, V
EE
= 2.5V
L1, L2 and L3 = equal length 50 impedance lines
R
T
= 50 terminator internal to scope
Decoupling 0.1 µF from GND to V
CC
and V
EE
All unused outputs are loaded with 50 to GND
C
L
= Fixture and stray capacitance 3 pF
FIGURE 1. AC Test Circuit
Notes:
For shift right mode, +1.05V is applied at S
0
.
The feedback path from output to input should be as short as possible.
FIGURE 2. Shift Frequency Test Circuit (Shift Left)
9 www.fairchildsemi.com
100336
Switching Waveforms
FIGURE 3. Propagation Delay (Clock) and Transition Times
FIGURE 4. Propagation Delay (Reset)

100336QCX

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Counter Shift Registers 4-Stage Ctr/Shft Reg
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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