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LTC3872IDDB-1#TRMPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC3872-1
10
38721f
For more information www.linear.com/LTC3872-1
to 30V or less, and the switch node can ring during the
turn-off of the MOSFET due to layout parasitics. Check
the switching waveforms of the MOSFET directly across
the drain and source terminals using the actual PC board
layout (not just on a lab breadboard!) for excessive ringing.
During the switch on-time, the control circuit limits the
maximum voltage drop across the power MOSFET to about
285mV, 105mV and 185mV at low duty cycle with IPRG
tied to V
IN
, GND, or left floating respectively. The peak
inductor current is therefore limited to (285mV, 105mV and
185mV)/R
DS(ON)
depending on the status of the IPRG pin.
The relationship between the maximum load current, duty
cycle and the R
DS(ON)
of the power MOSFET is:
R
DS(ON)
≤ V
SENSE(MAX)
•
1–D
MAX
1+
χ
2
•I
O(MAX)
•ρ
T
V
SENSE(MAX)
is the maximum voltage drop across the
power MOSFET. V
SENSE(MAX)
is typically 285mV, 185mV and
105mV. It is reduced with increasing duty cycle as shown
in Figure 3. The r
T
term accounts for the temperature co-
efficient of the R
DS(ON)
of the MOSFET, which is typically
0.4%/°C. Figure 4 illustrates the variation of normalized
R
DS(ON)
over temperature for a typical power MOSFET.
Another method of choosing which power MOSFET to
use is to check what the maximum output current is for a
given R
DS(ON)
, since MOSFET on-resistances are available
in discrete values.
I
O(MAX)
= V
SENSE(MAX)
•
1–D
MAX
1+
χ
2
•R
DS(ON)
•ρ
T
It is worth noting that the 1 – D
MAX
relationship between
I
O(MAX)
and R
DS(ON)
can cause boost converters with a
wide input range to experience a dramatic range of maxi-
mum input and output current. This should be taken into
consideration in applications where it is important to limit
the maximum current drawn from the input supply
.
Voltage on the NGATE pin should be within –0.3V to
(V
IN
+0.3V) limits. Voltage stress below –0.3V and above
V
IN
+ 0.3V can damage internal MOSFET driver, see Func-
tional Diagram. This is especially important in case of
driving MOSFETs with relatively high package inductance
(DPAK and bigger) or inadequate layout. A small Schottky
diode between NGATE pin and ground can prevent nega
-
tive voltage spikes. T
wo small Schottky diodes can inhibit
positive and negative voltage spikes (Figure 5).
JUNCTION TEMPERATURE (°C)
–50
ρ
T
NORMALIZED ON RESISTANCE
1.0
1.5
150
38721 F04
0.5
0
0
50
100
2.0
Figure 4. Normalized R
DS(ON)
vs Temperature
Figure 5
Figure 3. Maximum SENSE Threshold Voltage vs Duty Cycle
DUTY CYCLE (%)
1
0
MAXIMUM CURRENT SENSE VOLTAGE (mV)
50
100
150
200
250
300
20 40 60 80
38721 G03
100
IPRG = HIGH
IPRG = FLOAT
IPRG = LOW
applicaTions inForMaTion
SW
GND
V
IN
NGATE
38721 F04
LTC3872-1
SW
GND
V
IN
NGATE
LTC3872-1
LTC3872-1
11
38721f
For more information www.linear.com/LTC3872-1
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the power
MOSFET, the power dissipated by the device must be known.
This power dissipation is a function of the duty cycle, the
load current and the junction temperature itself (due to
the positive temperature coefficient of its R
DS(ON)
). As a
result, some iterative calculation is normally required to
determine a reasonably accurate value. Since the controller
is using the MOSFET as both a switching and a sensing
element, care should be taken to ensure that the converter
is capable of delivering the required load current over all
operating conditions (line voltage and temperature), and
for the worst-case specifications for V
SENSE(MAX)
and the
R
DS(ON)
of the MOSFET listed in the manufacturer’s data
sheet.
The power dissipated by the MOSFET in a boost converter is:
P
FET
=
I
O(MAX)
1– D
MAX
2
• R
DS(ON)
•D
MAX
• ρ
T
+k • V
O
1.85
•
I
O(MAX)
1– D
MAX
(
)
• C
RSS
• f
The first term in the equation above represents the I
2
R
losses in the device, and the second term, the switching
losses. The constant, k = 1.7, is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J
= T
A
+ P
FET
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the case to the ambient temperature (R
TH(CA)
). This value
of T
J
can then be compared to the original, assumed value
used in the iterative calculation process.
Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desired. The output
diode in a boost converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to the regulator output voltage.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to the
peak inductor current.
I
D(PEAK)
=I
L(PEAK)
= 1+
χ
2
•
I
O(MAX)
1–D
MAX
The power dissipated by the diode is:
P
D
= I
O(MAX)
• V
D
and the diode junction temperature is:
T
J
= T
A
+ P
D
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
Remember to keep the diode lead lengths short and to
observe proper switch-node layout (see Board Layout
Checklist) to avoid excessive ringing and increased dis
-
sipation.
Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct component
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL and bulk C) on the output voltage
ripple waveform are illustrated in Figure 6e for a typical
boost converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging
DV.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging DV. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
ESR
COUT
≤
0.01• V
O
I
IN(PEAK)
applicaTions inForMaTion
LTC3872-1
12
38721f
For more information www.linear.com/LTC3872-1
where:
I
IN(PEAK)
= 1+
χ
2
•
I
O(MAX)
1–D
MAX
For the bulk C component, which also contributes 1% to
the total ripple:
C
OUT
≥
I
O(MAX)
0.01• V
O
• f
For many designs it is possible to choose a single capacitor
type that satisfies both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved significantly by con
-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic capacitor can be used
to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform
should be verified on
a dedicated PC board (see Board
Layout section for more information on component place
-
ment). Lab breadboards generally suffer from excessive
series inductance (due to inter
-component wiring), and
these parasitics can
make the switching waveforms look
significantly worse than they would be on a properly
designed PC board.
The output capacitor in a boost regulator experiences
high RMS ripple currents, as shown in Figure 7. The RMS
output capacitor ripple current is:
I
RMS(COUT)
≈I
O(MAX)
•
V
O
– V
IN(MIN)
V
IN(MIN)
Note that the ripple current ratings from capacitor manu-
facturers are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than
required. Several capacitors may also be placed in parallel
to meet size or height requirements in the design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from
Sanyo has the lowest product of
ESR and size of any aluminum electrolytic, at a somewhat
higher price.
In surface mount applications, multiple capacitors may
have to be placed in parallel in order to meet the ESR or
RMS current handling requirements of the application.
Aluminum electrolytic and dry tantalum capacitors are
both available in surface mount packages. In the case of
tantalum, it is critical that the capacitors have been surge
tested for use in switching power supplies. An excellent
choice is AVX TPS series of surface mount tantalum. Also,
ceramic capacitors are now available with extremely low
ESR, ESL and high ripple current ratings.
V
IN
L D
SW
6a. Circuit Diagram
6b. Inductor and Input Currents
C
OUT
V
OUT
R
L
I
IN
I
L
6c. Switch Current
I
SW
t
ON
6d. Diode and Output Currents
6e. Output Voltage Ripple Waveform
I
O
I
D
V
OUT
(AC)
t
OFF
V
ESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
V
COUT
Figure 6. Switching Waveforms for a Boost Converter
applicaTions inForMaTion
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LTC3872IDDB-1#TRMPBF

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Description:
Switching Voltage Regulators No RSENSE C Mode Boost DC/DC Cntr
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