© 1999 Fairchild Semiconductor Corporation DS010630 www.fairchildsemi.com
January 1990
Revised November 1999
74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
74ACTQ533
Quiet Series Octal Transparent Latch
with 3-STATE Outputs
General Description
The ACTQ533 consists of eight latches with 3-STATE out-
puts for bus organized system applications. The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data satisfying the input tim-
ing requirements is latched. Data appears on the bus when
the Output Enable (OE) is LOW. When OE is HIGH, the
bus output is in the high impedance state.
The ACTQ533 utilizes Fairchild Quiet Series technology
to guarantee quiet output switching and improve dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a
split ground bus for superior performance.
Features
■ I
CC
and I
OZ
reduced by 50%
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch up immunity
■ Eight latches in a single package
■ 3-STATE outputs drive bus lines or buffer memory
address registers
■ Outputs source/sink 24 mA
■ Inverted version of the ACTQ373
■ 4 kV minimum ESD immunity
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT, FACT Quiet Series, and GTO are trademarks of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACTQ533SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
74ACTQ533MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ533PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Pin Names Description
D
0
–D
7
Data Inputs
LE Latch Enable Input
OE
Output Enable Input
O
0
–O
7
3-STATE Latch Outputs