LTM8057
13
8057f
For more information www.linear.com/LTM8057
APPLICATIONS INFORMATION
A few rules to keep in mind are:
1. Place the R
ADJ
resistor as close as possible to their
respective pins.
2. Place the C
IN
capacitor as close as possible to the V
IN
and GND connections of the LTM8057.
3. Place the C
OUT1
capacitor as close as possible to V
OUT
and V
OUT
.
4. Place the C
IN
and C
OUT
capacitors such that their
ground current flow directly adjacent or underneath
the LTM8057.
5. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8057.
Table 2. Safety Rated Capacitors
MANUFACTURER PART NUMBER DESCRIPTION
Murata
Electronics
GA343DR7GD472KW01L 4700pF, 250V AC,X7R,
4.5mm × 3.2mm
Capacitor
Johanson
Dielectrics
302R29W471KV3E-****-SC 470pF, 250V AC,X7R,
4.5mm × 2mm
Capacitor
Syfer Technology 1808JA250102JCTSP 100pF, 250V AC, C0G,
1808 Capacitor
PCB Layout
Most of the headaches associated with PCB layout have
been alleviated or even eliminated by the high level of
integration of the LTM8057. The LTM8057 is neverthe
-
less a switching power supply, and care must be taken to
minimize electrical noise to ensure proper operation. Even
with the high level of integration, you may fail to achieve
specified operation with a haphazard or poor layout. See
Figure 3 for a
suggested layout. Ensure that the grounding
and heat sinking are acceptable.
Figure 3. Layout Showing Suggested External Components, Planes and Thermal Vias
8057 F03
BIAS
RUN
ADJ
LTM8058
SS
C
BIAS
C
OUT1
V
OUT
V
IN
V
OUT
C
IN
THERMAL/INTERCONNECT VIAS
LTM8057
14
8057f
For more information www.linear.com/LTM8057
APPLICATIONS INFORMATION
6. Use vias to connect the GND copper area to the board’s
internal ground planes. Liberally distribute these GND
vias to provide both a good ground connection and
thermal path to the internal planes of the printed circuit
board. Pay attention to the location and density of the
thermal vias in Figure 3. The LTM8057 can benefit from
the heat sinking afforded by vias that connect to internal
GND planes at these locations, due to their proximity
to internal power handling components. The optimum
number of thermal vias depends upon the printed
circuit board design. For example, a board might use
very small via holes. It should employ more thermal
vias than a board that uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of the LTM8057. However, these capaci
-
tors can cause problems if the LTM8057 is plugged into a
live
supply
(see Linear Technology Application Note 88 for
a complete discussion). The low loss ceramic capacitor
combined with stray inductance in series with the power
source forms an underdamped tank circuit, and the volt
-
age at the V
IN
pin of the LTM8057 can ring to more than
twice the nominal input voltage, possibly exceeding the
LTM8057’s rating and damaging the part. If the input
supply is poorly controlled or the user will be plugging
the LTM8057 into an energized supply, the input network
should be designed to prevent this overshoot. This can be
accomplished by installing a small resistor in series to V
IN
,
but the most popular method of controlling input voltage
overshoot is adding an electrolytic bulk capacitor to the
V
IN
net. This capacitors relatively high equivalent series
resistance damps the circuit and eliminates the voltage
overshoot. The extra capacitor improves low frequency
ripple filtering and can slightly improve the efficiency of the
circuit, though it can be a large component in the circuit.
Thermal Considerations
The LTM8057 output current may need to be derated if it
is required to operate in a high ambient temperature. The
amount of current derating is dependent upon the input
voltage, output power and ambient temperature. The
temperature rise curves given in the Typical Performance
Characteristics section can be used as a guide. These curves
were generated by the LTM8057 mounted to a 58cm
2
4-layer FR4 printed circuit board. Boards of other sizes
and layer count can exhibit different thermal behavior, so
it is incumbent upon the user to verify proper operation
over the intended system’s line, load and environmental
operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
θ
JA
: Thermal resistance from junction to ambient
θ
JCbottom
: Thermal resistance from junction to the bot-
tom of the product case
θ
JCtop
: Thermal resistance from junction to top of the
product case
θ
JCboard
: Thermal resistance from junction to the printed
circuit board.
While the meaning of each of these coefficients may seem
to be intuitive, JEDEC has defined each to avoid confu
-
sion and inconsistency. These definitions are given in
JESD 51-12, and are quoted or paraphrased as follows:
θ
JA
is the natural convection junction-to-ambient air
thermal resistance measured in a one cubic foot sealed
enclosure. This environment is sometimes referred to
as still air although natural convection causes the air to
move. This value is determined with the part mounted to a
JESD 51-9 defined test board, which does not reflect an
actual application or viable operating condition.
θ
JCbottom
is the junction-to-board thermal resistance with
all of the component power dissipation flowing through the
bottom of the package. In the typical µModule converter,
the bulk of the heat flows out the bottom of the package,
but there is always heat flow out into the ambient envi
-
ronment. As a result, this thermal resistance value may
be
useful
for comparing packages but the test conditions
don’t generally match the users application.
LTM8057
15
8057f
For more information www.linear.com/LTM8057
APPLICATIONS INFORMATION
θ
JCtop
is determined with nearly all of the component power
dissipation flowing through the top of the package. As the
electrical connections of the typical µModule converter are
on the bottom of the package, it is rare for an application
to operate such that most of the heat flows from the junc
-
tion to the top of the part. As in the case of θ
JCbottom
, this
value may be useful for comparing packages but the test
conditions don’t generally match the users application.
θ
JCboard
is the junction-to-board thermal resistance where
almost all of the heat flows through the bottom of the
µModule converter and into the board, and is really the
sum of the θ
JCbottom
and the thermal resistance of the
bottom of the part through the solder joints and through a
portion of the board. The board temperature is measured
a specified distance from the package, using a two-sided,
two-layer board. This board is described in JESD 51-9.
Given these definitions, it should now be apparent that none
of these thermal coefficients reflects an actual physical
operating condition of a µModule converter. Thus, none
of them can be individually used to accurately predict the
thermal performance of the product. Likewise, it would
be inappropriate to attempt to use any one coefficient to
correlate to the junction temperature vs load graphs given
in the product’s data sheet. The only appropriate way to
use the coefficients is when running a detailed thermal
analysis, such as FEA, which considers all of the thermal
resistances simultaneously.
A graphical representation of these thermal resistances
is given in Figure 4.
The blue resistances are contained within the µModule
converter, and the green are outside.
The die temperature of the LTM8057 must be lower than
the maximum rating of 125°C, so care should be taken in
the layout of the circuit to ensure good heat sinking of the
LTM8057. The bulk of the heat flow out of the LTM8057
is through the bottom of the module and the BGA pads
into the printed circuit board. Consequently a poor printed
circuit board design can cause excessive heating, result
-
ing in impaired performance or reliability. Please refer to
the PCB Layout section for printed circuit board design
suggestions.
Figure 4
8057 F04
µMODULE DEVICE
JUNCTION-TO-CASE (TOP)
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
CASE (TOP)-TO-AMBIENT
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
JUNCTION
AMBIENT
CASE (BOTTOM)-TO-BOARD
RESISTANCE

LTM8057IY#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 2kVAC Isolated, 1.5W Module DC/DC Converter
Lifecycle:
New from this manufacturer.
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