www.vishay.com Document Number: 90362
4 S11-1045-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT
www.vishay.com/doc?91000
IRFSL9N60A, SiHFSL9N60A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
0
400
800
1200
1600
2000
2400
1101001000
C, Capacitance (pF)
DS
V , Drain-to-Source Volta
A
V = 0V, f = 1MH z
C = C + C , C S HOR TED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0 10 20 30 40 50
0
4
8
12
16
20
Q , Total Gate Charge (nC)
V , Gate-to-Source Voltage (V)
G
GS
FOR TEST CIRCUIT
SEE FIGURE
I =
D
13
9.2A
V = 120V
DS
V = 300V
DS
V = 480V
DS
400V
0.1
1
10
100
0.2 0.5 0.7 1.0 1.2
V ,Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
V = 0 V
GS
T = 25 C
J
°
T = 150 C
J
°
0.1
1
10
100
1000
10 100 1000 10000
OPERATION IN THIS AREA LIMITED
BY R
DS(on)
Sin
le Pulse
T
T
= 150 C
= 25 C
°
°
J
C
V , Drain-to-Source Volta
e (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms