ZL38001 Data Sheet
30
Zarlink Semiconductor Inc.
5.0 Register Summary
Bit Name Description
7 LIMIT When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC
register and when low 2-bit shift mode is disabled. Default limit for Rin and
Sin is 3.14 dBm0.
6
MUTE_R When high, the Rin path is muted to quite code (after the NLP) and when low
the Rin path is not muted.
5
MUTE_S When high, the Sin path is muted to quite code (after the NLP) and when low
the Sin path is not muted.
4
BYPASS When high, the Send and Receive paths are transparently by-passed from
input to output and when low the Send and Receive paths are not bypassed.
3
NB- When high, Narrowband signal detectors in Rin and Sin paths are disabled
and when low the signal detectors are enabled.
2
AGC- When high, AGC is disabled and when low AGC is enabled.
1
AH- When high, the Howling detector is disabled and when low the Howling
detector is enabled.
0
RESET When high, the power initialization routine is executed presetting all registers
to default values.
This bit automatically clears itself to ’0’ when reset is complete.
Register Table 1 - Main Control Register (MC)
Bit Name Description
7 P- When high, the Exponential weighting function for the adaptive filter is
disabled and when low the weighting function is enabled
6 ASC- When high, the Internal Adaptation speed control is disabled and when low
the Adaptation speed is enabled.
5 NLP- When high, the Non Linear Processor is disabled in the Sin/Sout path and
when low the NLP is enabled.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC)
External Read/Write Address: 00
H
Reset Value: 00
H
76543210
LIMIT
MUTE_R MUTE_S BYPASS NB- AGC- AH- RESET
External Read/Write Address:21
H
Reset Value: 00
H
76543210
P- ASC- NLP- INJ- HPF- HCLR ADAPT- ECBY
