ZL38001 Data Sheet
40
Zarlink Semiconductor Inc.
Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2)
Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1)
Bit Name Description
7SIPD
15
These peak detector registers allow the user to monitor the receive in signal
(Sin) peak level at reference point S1 (see Figure 1). The information is in 16-
bit 2’s complement linear coded format presented in two 8-bit registers. The
high byte is in Register 2 and the low byte is in Register 1.
6SIPD
14
5SIPD
113
4SIPD
12
3SIPD
11
2SIPD
10
1SIPD
9
0SIPD
8
Bit Name Description
7 SEPD
7
These peak detector registers allow the user to monitor the error signal peak
level in the send path at reference point S2 (see Figure 1). The information is
in 16-bit 2’s complement linear coded format presented in two 8-bit registers.
The high byte is in Register 2 and the low byte is in Register 1.
6 SEPD
6
5 SEPD
5
4 SEPD
4
3 SEPD
3
2 SEPD
2
1 SEPD
1
0 SEPD
0
External Read Address: 37
H
Reset Value: 00
H
76543210
SIPD
15
SIPD
14
SIPD
13
SIPD
12
SIPD
11
SIPD
10
SIPD
9
SIPD
8
External Read Address: 38
H
Reset Value: 00
H
76543210
SEPD
7
SEPD
6
SEPD
5
SEPD
4
SEPD
3
SEPD
2
SEPD
1
SEPD
0
