MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
10 ______________________________________________________________________________________
Applications Information
Static and Dynamic
Performance Definitions
Integral Nonlinearity
Integral nonlinearity (INL) (Figure 5a) is the deviation of
the values on an actual transfer function from either a
best-straight-line fit (closest approximation to the actual
transfer curve) or a line drawn between the endpoints
of the transfer function once offset and gain errors have
been nullified. For a DAC, the deviations are measured
every single step.
Differential Nonlinearity
Differential nonlinearity (DNL) (Figure 5b) is the differ-
ence between an actual step height and the ideal value
of 1LSB. A DNL error specification of less than 1LSB
guarantees no missing codes and a monotonic transfer
function.
Table 1. Power-Down Mode Selection
X = Don’t care.
9.6k
Ω
*
I
FS
0.1
μ
F10
μ
F
DV
DD
R
SET
REFR
AV
DD
REFO
1.2V
BANDGAP
REFERENCE
REN
DGND
AGND
AGND
CURRENT-
SOURCE ARRAY
EXTERNAL
1.2V
REFERENCE
*9.6k
Ω
REFERENCE CURRENT-SET RESISTOR
INTERNAL TO MAX5184 ONLY. USE EXTERNAL
R
SET
FOR MAX5181.
MAX5181
MAX5184
MAX6520
Figure 3. MAX5181/MAX5184 with External Reference
Wake-Up
High-Z
High-Z
MAX5181
MAX5181
AGNDMAX5184
ShutdownX1
Last state prior to standby mode10
AGND
MAX5184
Standby00
OUTPUT STATEPOWER-DOWN MODEDACEN (DAC ENABLE)
PD
(POWER-DOWN SELECT)
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
______________________________________________________________________________________ 11
Offset Error
Offset error (Figure 5c) is the difference between the
ideal and the actual offset point. For a DAC, the offset
point is the step value when the digital input is zero.
This error affects all codes by the same amount and
can usually be compensated by trimming.
Gain Error
Gain error (Figure 5d) is the difference between the
ideal and the actual full-scale output voltage on the
transfer curve, after nullifying the offset error. This error
alters the slope of the transfer function and corre-
sponds to the same percentage error in each step.
Settling Time
Settling time is the amount of time required from the start
of a transition until the DAC output settles its new output
value to within the converter’s specified accuracy.
Digital Feedthrough
Digital feedthrough is the noise generated on a DAC’s
output when any digital input transitions. Proper board
layout and grounding will significantly reduce this
noise, but there will always be some feedthrough
caused by the DAC itself.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the input signal’s first four harmonics to the fun-
damental itself. This is expressed as:
where V
1
is the fundamental amplitude, and V
2
through
V
5
are the amplitudes of the 2nd- through 5th-order
harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion com-
ponent.
Differential to Single-Ended Conversion
The MAX4108 low-distortion, high-input bandwidth
amplifier may be used to generate a voltage from the
array current output of the MAX5181. The differential
voltage across OUTP and OUTN is converted into a
single-ended voltage by designing an appropriate
operational amplifier configuration (Figure 6).
I/Q Reconstruction
in a QAM Application
The low-distortion performance of two MAX5181/
MAX5184s supports analog reconstruction of in-phase
(I) and quadrature (Q) carrier components typically
used in quadrature amplitude modulation (QAM) archi-
tectures where two separate buses carry the I and Q
data. A QAM signal is both amplitude (AM) and phase
modulated, created by summing two independently
modulated carriers of identical frequency but different
phase (90° phase difference).
In a typical QAM application (Figure 7), the modulation
occurs in the digital domain, and two DACs such as the
MAX5181/MAX5184 may be used to reconstruct the
analog I and Q components.
THD 20 log
(V V V V )
V
2
2
3
2
4
2
5
2
1
+++
Figure 4. Timing Diagram
CLK
D0–D9
OUT N - 1
N - 1
N
N
N + 1
N + 1
t
DS
t
DH
t
CH
t
CL
t
CLK
MAX5181/MAX5184
10-Bit, 40MHz, Current/Voltage-Output DACs
12 ______________________________________________________________________________________
The I/Q reconstruction system is completed by a quad-
rature modulator that combines the reconstructed com-
ponents with in-phase and quadrature carrier
frequencies and then sums both outputs to provide the
QAM signal.
Using the MAX5181/MAX5184 for
Arbitrary Waveform Generation
Designing a traditional arbitrary waveform generator
(AWG) requires five major functional blocks (Figure 8a):
clock generator, counter, waveform memory, DAC for
waveform reconstruction, and output filter. The wave-
form memory contains the sequentially stored digital
replica of the desired analog waveforms. This memory
shares a common clock with the DAC.
For each clock cycle, a counter adds one count to the
address for the waveform memory. The memory then
loads the next value to the DAC, which generates an
analog output voltage corresponding to that data value.
A DAC output filter can either be a simple or complex
lowpass filter, depending on the AWG requirements for
waveform function and frequencies. The main limita-
tions of the AWG’s flexibility are DAC resolution and
dynamic performance, memory length, clock frequen-
cy, and the filter characteristics.
Although the MAX5181/MAX5184 offer high-frequency
operation and excellent dynamics, they are suitable for
relaxed requirements in resolution (10-bit AWGs). To
increase an AWG’s high-frequency accuracy, tempera-
0
2
1
4
3
7
6
5
000 010001 011 100 101 110
AT STEP
011 (1/2 LSB )
AT STEP
001 (1/4 LSB )
111
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
0
2
1
4
3
6
5
000 010001 011 100 101
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1 LSB
1 LSB
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 5a. Integral Nonlinearity Figure 5b. Differential Nonlinearity
0
2
1
3
000 010001 011
ACTUAL
DIAGRAM
IDEAL DIAGRAM
ACTUAL
OFFSET
POINT
OFFSET ERROR
(+1 1/4 LSB)
IDEAL OFFSET
POINT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
0
5
4
6
7
000 101100 110 111
IDEAL DIAGRAM
GAIN ERROR
(-1 1/4 LSB)
IDEAL FULL-SCALE OUTPUT
ACTUAL
FULL-SCALE
OUTPUT
DIGITAL INPUT CODE
ANALOG OUTPUT VALUE
Figure 5c. Offset Error Figure 5d. Gain Error

MAX5184BEEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 10-Bit High Speed DAC
Lifecycle:
New from this manufacturer.
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