ISL89160, ISL89161, ISL89162
10
FN7719.3
February 20, 2013
Typical Application Circuit
This is an example of how the ISL89160, ISL89161, ISL89162,
MOSFET drivers can be applied in a zero voltage switching full
bridge. Two main signals are required: a 50% duty cycle square
wave (SQR) and a PWM signal synchronized to the edges of the
SQR input. An ISL89162 is used to drive T1 with alternating half
cycles driving Q
UL
and Q
UR
. An ISL89160 is used to drive Q
LL
and
Q
LR
also with alternating half cycles. Unlike the two high-side
bridge FETs, the two low side bridge FETs are turned on with a
rising edge delay. The delay is setup by the RCD network on the
inputs to the ISL89160. The duration of the delay is chosen to
turn on the low-side FETs when the voltage on their respective
drains is at the resonant valley. For a complete description of the
ZVS topology, refer to AN1603
“ISL6752_54 Evaluation Board
Application Note”.
General PCB Layout Guidelines
The AC performance of the ISL89160, ISL89161, ISL89162
depends significantly on the design of the PC board. The
following layout design guidelines are recommended to achieve
optimum performance:
• Place the driver as close as possible to the driven power FET.
• Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
• Keep power loops as short as possible by paralleling the
source and return traces.
• Use planes where practical; they are usually more effective
than parallel traces.
• Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
noise voltages in the low level signal lines.
• When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
• Be aware of magnetic fields emanating from transformers and
inductors. Gaps in these structures are especially bad for
emitting flux.
• If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
coupling.
• The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
• Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
• It may be necessary to add resistance to dampen resonating
parasitic circuits especially on OUTA and OUTB. If an external
gate resistor is unacceptable, then the layout must be
improved to minimize lead inductance.
• Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
that source the input signals to the ISL89160, ISL89161,
ISL89162.
• Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
• Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
• Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated. This must be accounted for in the PCB
layout and circuit design.
• If you simulate your circuits, consider including parasitic
components especially parasitic inductance.
V
LL
PWM
LR
LL
LL
Red dashed lines
emphasize the
resonant switching
delay of the low-
side bridge FETs
ZVS FULL BRIDGE
T1A
T1B
T2
U1B
U2A U2B
Q
UL
Q
UR
Q
LL
Q
LR
LL LR
V
LR
SQR
SQR
R
V
GLL
V
GUL
V
GLR
V
GUR
V
GLR
V
GUL
V
GUR
V
GLL
V
BRIDGE
ISL89162
U1A
½ ISL89160 ½ ISL89160
LL: Lower Left
LR: Lower Right
UL: Upper Left
UR: Upper Right
GLL: Gate Lower Left
