ISL89160, ISL89161, ISL89162
9
FN7719.3
February 20, 2013
In Figure 16, R
del
and C
del
delay the rising edge of the input
signal. For the falling edge of the input signal, the diode shorts
out the resistor resulting in a minimal falling edge delay. If the
diode polarity is reversed, the falling edge is delayed and the
rising delay is minimal.
The 37% and 63% thresholds were chosen to simplify the
calculations for the desired time delays. When using an RC
circuit to generate a time delay, the delay is simply T (secs) = R
(ohms) x C (farads). Please note that this equation only applies if
the input logic voltage amplitude is 3.3V. If the logic high
amplitude is higher than 3.3V, the equations in Equation 1 can
be used for more precise delay calculations.
In this example, the high input logic voltage is 5V, the positive
threshold is 63% of 3.3V and the low level input logic is 0.1V.
Note the rising edge propagation delay of the driver must be
added to this value.
The minimum recommended value of C is 100pF. The parasitic
capacitance of the PCB and any attached scope probes will
introduce significant delay errors if smaller values are used.
Larger values of C will further minimize errors.
Acceptable values of R are primarily effected by the source
resistance of the logic inputs. Generally, 100Ω resistors or larger
are usable. A practical maximum value, limited by contamination
on the PCB, is 1MΩ
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL89160 and ISL89161
is less than 1ns. The matching is so precise that carefully
matched and calibrated scopes probes and scope channels must
be used to make this measurement. Because of this excellent
performance, these driver outputs can be safely paralleled to
double the current drive capacity. It is important that the INA and
INB inputs be connected together on the PCB with the shortest
possible trace. This is also required of OUTA and OUTB. Note that
the ISL89162 cannot be paralleled because of the
complementary logic.
Power Dissipation of the Driver
The power dissipation of the ISL89160, ISL89161, ISL89162 is
dominated by the losses associated with the gate charge of the
driven bridge FETs and the switching frequency. The internal bias
current also contributes to the total dissipation but is usually not
significant as compared to the gate charge losses.
Figure 17 illustrates how the gate charge varies with the gate
voltage in a typical power MOSFET. In this example, the total gate
charge for V
gs
= 10V is 21.5nC when V
DS
= 40V. This is the
charge that a driver must source to turn-on the MOSFET and
must sink to turn-off the MOSFET.
Equation 2 shows calculating the power dissipation of the driver:
where:
freq = Switching frequency,
V
GS
= V
DD
bias of the ISL89160, ISL89161, ISL89162
Q
c
= Gate charge for V
GS
I
DD
(freq) = Bias current at the switching frequency (see
Figure 10)
r
DS(ON)
= ON-resistance of the driver
R
gate
= External gate resistance (if any).
Note that the gate power dissipation is proportionally shared with
the external gate resistor and the output r
DS(ON)
. When sizing an
external gate resistor, do not overlook the power dissipated by
this resistor.
FIGURE 16. DELAY USING RCD NETWORK
V
H
5V=
V
THRESH
63% 3.3V=
V
L
0.1V=
R
del
100=
C
del
1nF=
t
del
R
del
C
del
–
LN
V
L
V
THRESH
–
V
H
V
L
–
--------------------------------------------
1+
=
t
del
51.731ns=
High level of the logic signal into the RC
Positive going threshold
Low level of the logic signal into the RC
Timing values
Nominal delay time
(EQ. 1)
Q
g,
GATE CHARGE (nC)
12
10
8
6
4
2
0
024681012141618202224
V
gs
GATE-SOURCE VOLTAGE (V)
FIGURE 17. MOSFET GATE CHARGE vs GATE VOLTAGE
V
DS
= 64V
V
DS
= 40V
(EQ. 2)
P
D
2Q
c
freq V
GS
R
gate
R
gate
r
DS ON
+
---------------------------------------------
I
DD
freqV
DD
+=
