IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
20
Byte 0 FS Readback and PLL Selection Register
Bit Pin Name Description Type Default
7
-
FSLC CPU Freq. Sel. Bit (Most Significant)
R
Latch
6
-
FSLB CPU Fre
. Sel. Bit
R
Latch
5
-
FSLA CPU Freq. Sel. Bit (Least Significant)
R
Latch
4- iAMT_EN
Set via SMBus or dynamically by CK505 if detects
d
namic M1
RW 0
3 Reserved Reserved RW 0
2 - SRC_Main_SEL Select source for SRC Main RW 0
1 - SATA_SEL Select source for SATA clock R
0
0- PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-on
and go to latches open state
This bit is ignored and treated at '1' if device is in iAMT
mode.
RW 1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin Name Description Type Default
7 13/14 SRC0_SEL Select SRC0 or DOT96 R
0
6 - PLL1_SSC_SEL Select 0.5% down or center SSC R
0
5 PLL3_SSC_SEL Select 0.5% down or center SSC RW 0
4 PLL3_CF3 PLL3 Quick Config Bit 3 RW 0
3 PLL3_CF2 PLL3 Quick Confi
Bit 2 R
0
2 PLL3_CF1 PLL3 Quick Config Bit 1 RW 0
1 PLL3_CF0 PLL3 Quick Config Bit 0 RW 1
0 PCI_SEL PCI_SEL RW 1
Byte 2 Output Enable Register
Bit Pin Name Description Type Default
7 REF_OE Output enable for REF, if disabled output is tri-stated RW 1
6 USB_OE Output enable for USB RW 1
5 PCIF5_OE Out
ut enable for PCI5 R
1
4 PCI4_OE Output enable for PCI4 RW 1
3 PCI3_OE Output enable for PCI3 RW 1
2 PCI2_OE Out
ut enable for PCI2 R
1
1 PCI1_OE Output enable for PCI1 RW 1
0 PCI0_OE Output enable for PCI0 RW 1
Byte 3 Output Enable Register
Bit Pin Name Description Type Default
7 SRC11_OE Output enable for SRC11 RW 1
6 SRC10_OE Out
ut enable for SRC10 R
1
5 SRC9_OE Output enable for SRC9 RW 1
4 SRC8/ITP_OE Output enable for SRC8 or ITP RW 1
3 SRC7_OE Out
ut enable for SRC7 R
1
2 SRC6_OE Output enable for SRC6 RW 1
1 SRC5_OE Output enable for SRC5 RW 1
0 SRC4_OE Output enable for SRC4 RW 1
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit Pin Name Description Type Default
7 SRC3_OE Out
ut enable for SRC3 R
1
6 SATA/SRC2_OE Output enable for SATA/SRC2 RW 1
5 SRC1_OE Output enable for SRC1 RW 1
4 SRC0/DOT96_OE Out
ut enable for SRC0/DOT96 R
1
3 CPU1_OE Output enable for CPU1 RW 1
2 CPU0_OE Output enable for CPU0 RW 1
1 PLL1_SSC_ON Enable PLL1's s
read modulation R
1
0 PLL3_SSC_ON Enable PLL3's spread modulation RW 1S
read Enabled
1
Output Disabled
S
read Disabled
S
read Disabled
Out
ut Enabled
Output Enabled
S
read Enabled
Output Disabled
Output Disabled
Out
ut Disabled
Output Disabled
Output Enabled
Output Enabled
Out
ut Enabled
Output Enabled
0
01
Out
ut Disabled
Out
ut Disabled
Output Enabled
Out
ut Enabled
Output Enabled
Output Enabled
Out
ut Enabled
Output Enabled
Output Enabled
Out
ut Enabled
Output Disabled
Out
ut Disabled
Output Disabled
Output Disabled
1
Output Disabled
Out
ut Disabled
Output Disabled
Output Disabled
Output Enabled
Output Enabled
Out
ut Enabled
Output Enabled
Output Enabled
Out
ut Enabled
Output Enabled
Output Enabled
Output Disabled
Output Disabled
Out
ut Disabled
Output Disabled
0
Output Disabled
Output Disabled
Out
ut Disabled
0
Down s
read
Down spread
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
DOT96
Center s
read
Center spread
SRC0
01
1
SATA = SRC_Main
Configuration Not Saved
iAMT Enabled
SRC Main = PLL3
See Table 1 : CPU Frequency Select Table
Legacy Mode
SRC Main = PLL1
Configuration Saved
SATA = PLL2
PCI from PLL1 PCI from SRC_MAIN