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9LPRS502SKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
22
Byte 10 CK505 Rev 0.85 functions (ICS Rev H silicon and higher)
Bit Pin Name Description Type Default
7 SRC5_EN Readback Readback of SRC5 enable latch
R
Latch
6 Reserved RW 0
5 Reserved RW 0
4 Reserved RW 0
3 Reserved RW 0
2 Reserved RW 0
1 CPU 1 Stop Enable Enables control of CPU1 with CPU_STOP# RW 1
0 CPU 0 Stop Enable Enables control of CPU 0 with CPU_STOP# RW 1
Byte 11 CK505 Rev 1.0 functions (ICS Rev P silicon and higher)
Bit Pin Name Description Type Default
7 Reserved RW 0
6 Reserved RW 0
5 Reserved RW 0
4 Reserved RW 0
3 CPU2_iAMT_EN Enables CPU2
(
ITP
)
out
p
ut in iAMT state
(
M1
)
RW 0
2 CPU1_iAMT_EN Enables CPU1 output in iAMT state (M1) RW 1
1 PCIe-Gen2 PCIe-Gen2 status
R
0
0 CPU2 Stop Enable Enables control of CPU2(ITP) with CPU_STOP# RW 1
Byte 12 Byte Count Register
Bit Pin Name Description Type Default
7 Reserved RW 0
6 Reserved RW 0
5 BC5 RW 0
4 BC4 RW 0
3 BC3 RW 1
2 BC2 RW 1
1 BC1 RW 0
0 BC0 RW 1
Byte 13 CK505 PLL1 M/N Programming Register
Bit Pin Name Description Type Default
7
N Div8 N Divider 8 RW X
6
N Div9 N Divider 9 RW X
5
M Div5 RW X
4
M Div4 RW X
3
M Div3 RW X
2
M Div2 RW X
1
M Div1 RW X
0
M Div0 RW X
Byte 14 CK505 PLL1 M/N Programming Register
Bit Pin Name Description Type Default
7
N Div7 RW X
6
N Div6 RW X
5
N Div5 RW X
4
N Div4 RW X
3
N Div3 RW X
2
N Div2 RW X
1
N Div1 RW X
0
N Div0 RW X
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
-
-
-
-
-
-
-
-
-
-
-
01
-
-
Sto
pp
able
01
Off in iAMT
non-Gen2
Free Runnin
g
TBD
TBD
TBD
TBD
Free runnin
g
in iAMT
Free running in iAMT
PCIe Gen2 compliant
TBD
TBD
TBD
Off in iAMT
Sto
pp
able
01
TBD
TBD
Free Running
Free Runnin
g
SRC5 Enabled
TBD
TBD
TBD
TBD
TBD
Stoppable
TBD
TBD
TBD
TBD
01
CPU/PCI Sto
p
Enabled
The decimal representation of M and N Divider in Byte
13 and 14 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
-
-
-
The decimal representation of M and N Divider in Byte
13 and 14 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
Read Back byte count register,
max bytes = 32
Reserved
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
23
Byte 15 CK505 PLL1 Spread Spectrum Control Register
Bit Pin Name Description Type Default
7
SSP7 RW X
6
SSP6 RW X
5
SSP5 RW X
4
SSP4 RW X
3
SSP3 RW X
2
SSP2 RW X
1
SSP1 RW X
0
SSP0 RW X
Byte 16 CK505 PLL1 Spread Spectrum Control Register
Bit Pin Name Description Type Default
7
Reserved Reserved RW 0
6
SSP14 RW x
5
SSP13 RW X
4
SSP12 RW X
3
SSP11 RW X
2
SSP10 RW X
1
SSP9 RW X
0
SSP8 RW X
Byte 17 CK505 PLL3 M/N Programming Register
Bit Pin Name Description Type Default
7
N Div8 N Divider 8 RW X
6
N Div9 N Divider 9 RW X
5
M Div5 RW X
4
M Div4 RW X
3
M Div3 RW X
2
M Div2 RW X
1
M Div1 RW X
0
M Div0 RW X
Byte 18 CK505 PLL3 M/N Programming Register
Bit Pin Name Description Type Default
7
N Div7 RW X
6
N Div6 RW X
5
N Div5 RW X
4
N Div4 RW X
3
N Div3 RW X
2
N Div2 RW X
1
N Div1 RW X
0
N Div0 RW X
Byte 19 CK505 PLL3 Spread Spectrum Control Register
Bit Pin Name Description Type Default
7
SSP7 RW X
6
SSP6 RW X
5
SSP5 RW X
4
SSP4 RW X
3
SSP3 RW X
2
SSP2 RW X
1
SSP1 RW X
0
SSP0 RW X
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
-
The decimal representation of M and N Divider in Byte
17 and 18 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
The decimal representation of M and N Divider in Byte
17 and 18 will configure the VCO frequency. Default
at power up = latch-in or Byte 0 Rom table.
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
24
Byte 20 CK505 PLL3 Spread Spectrum Control Register
Bit Pin Name Description Type Default
7
Reserved Reserved RW 0
6
SSP14 RW X
5
SSP13 RW X
4
SSP12 RW X
3
SSP11 RW X
2
SSP10 RW X
1
SSP9 RW X
0
SSP8 RW X
Byte 21 M/N Enables
Bit Pin Name Description Type Default
7
Reserved RW 0
6
Reserved RW 0
5
Reserved RW 0
4
Reserved RW 0
3
Reserved RW 0
2
Reserved RW 0
1 M/N Enable CPU
RW
0
0 M/N Enable RW 0
Byte 22 CPU M/N Programming
Bit Pin Name Description
Type
Default
7 N Div bit 8 PLL 1 M/N Programming RW X
6 N Div bit 9 (Intel PLL1 CPU) RW X
5M Div Bit 5 RW X
4M Div Bit 4 RW X
3M Div Bit 3 RW X
2M Div Bit 2 RW X
1M Div Bit 1 RW X
0M Div Bit 0 RW X
Byte 23 CPU M/N Programming
Bit Pin Name Description
Type
Default
7 N Div bit 7 PLL 1 M/N Programming RW X
6 N Div bit 6 (Intel PLL1 CPU) RW X
5 N Div bit 5 RW X
4 N Div bit 4 RW X
3 N Div bit 3 RW X
2 N Div bit 2 RW X
1 N Div bit 1 RW X
0N Div Bit 0 RW X
Bytes 24-62 Reserved
Byte 63 Special Power Management Features (Rev P Silicon and Higher)
Bit Pin Name Description RW Default
7
Reserved RW 0
6
Reserved RW 0
5
Reserved RW 0
4
Reserved RW 0
3
Reserved RW 0
2
Reserved RW 0
1 SATA PLL Power Management Feature RW Note
0 XTAL PD Control Controls XTAL on/off in legacy PD RW 1
These Spread Spectrum bits will program the spread
pecentage. Contact ICS for the correct values.
01
--
-
-
-
-
-
-
-
-
-
-
-
-
-
-
01
Disable
Enable
Disable Enable
01
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
-
-
0
-
-
-
-
-
01
*Accessing any SMBus bytes not shown in the datasheet could result in incorrect clock functions.
off on
off on
Note: Default is "off" for Rev P Silicon and higher.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

9LPRS502SKLFT

Mfr. #:
Buy 9LPRS502SKLFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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