OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

9LPRS502SFLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
19
General SMBus serial interface information for the ICS9LPRS502
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the beginning byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byte
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
20
Byte 0 FS Readback and PLL Selection Register
Bit Pin Name Description Type Default
7
-
FSLC CPU Freq. Sel. Bit (Most Significant)
R
Latch
6
-
FSLB CPU Fre
q
. Sel. Bit
R
Latch
5
-
FSLA CPU Freq. Sel. Bit (Least Significant)
R
Latch
4- iAMT_EN
Set via SMBus or dynamically by CK505 if detects
d
y
namic M1
RW 0
3 Reserved Reserved RW 0
2 - SRC_Main_SEL Select source for SRC Main RW 0
1 - SATA_SEL Select source for SATA clock R
W
0
0- PD_Restore
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-on
and go to latches open state
This bit is ignored and treated at '1' if device is in iAMT
mode.
RW 1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin Name Description Type Default
7 13/14 SRC0_SEL Select SRC0 or DOT96 R
W
0
6 - PLL1_SSC_SEL Select 0.5% down or center SSC R
W
0
5 PLL3_SSC_SEL Select 0.5% down or center SSC RW 0
4 PLL3_CF3 PLL3 Quick Config Bit 3 RW 0
3 PLL3_CF2 PLL3 Quick Confi
g
Bit 2 R
W
0
2 PLL3_CF1 PLL3 Quick Config Bit 1 RW 0
1 PLL3_CF0 PLL3 Quick Config Bit 0 RW 1
0 PCI_SEL PCI_SEL RW 1
Byte 2 Output Enable Register
Bit Pin Name Description Type Default
7 REF_OE Output enable for REF, if disabled output is tri-stated RW 1
6 USB_OE Output enable for USB RW 1
5 PCIF5_OE Out
p
ut enable for PCI5 R
W
1
4 PCI4_OE Output enable for PCI4 RW 1
3 PCI3_OE Output enable for PCI3 RW 1
2 PCI2_OE Out
p
ut enable for PCI2 R
W
1
1 PCI1_OE Output enable for PCI1 RW 1
0 PCI0_OE Output enable for PCI0 RW 1
Byte 3 Output Enable Register
Bit Pin Name Description Type Default
7 SRC11_OE Output enable for SRC11 RW 1
6 SRC10_OE Out
p
ut enable for SRC10 R
W
1
5 SRC9_OE Output enable for SRC9 RW 1
4 SRC8/ITP_OE Output enable for SRC8 or ITP RW 1
3 SRC7_OE Out
p
ut enable for SRC7 R
W
1
2 SRC6_OE Output enable for SRC6 RW 1
1 SRC5_OE Output enable for SRC5 RW 1
0 SRC4_OE Output enable for SRC4 RW 1
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit Pin Name Description Type Default
7 SRC3_OE Out
p
ut enable for SRC3 R
W
1
6 SATA/SRC2_OE Output enable for SATA/SRC2 RW 1
5 SRC1_OE Output enable for SRC1 RW 1
4 SRC0/DOT96_OE Out
p
ut enable for SRC0/DOT96 R
W
1
3 CPU1_OE Output enable for CPU1 RW 1
2 CPU0_OE Output enable for CPU0 RW 1
1 PLL1_SSC_ON Enable PLL1's s
p
read modulation R
W
1
0 PLL3_SSC_ON Enable PLL3's spread modulation RW 1S
p
read Enabled
1
Output Disabled
S
p
read Disabled
S
p
read Disabled
Out
p
ut Enabled
Output Enabled
S
p
read Enabled
Output Disabled
Output Disabled
Out
p
ut Disabled
Output Disabled
Output Enabled
Output Enabled
Out
p
ut Enabled
Output Enabled
0
01
Out
p
ut Disabled
Out
p
ut Disabled
Output Enabled
Out
p
ut Enabled
Output Enabled
Output Enabled
Out
p
ut Enabled
Output Enabled
Output Enabled
Out
p
ut Enabled
Output Disabled
Out
p
ut Disabled
Output Disabled
Output Disabled
1
Output Disabled
Out
p
ut Disabled
Output Disabled
Output Disabled
Output Enabled
Output Enabled
Out
p
ut Enabled
Output Enabled
Output Enabled
Out
p
ut Enabled
Output Enabled
Output Enabled
Output Disabled
Output Disabled
Out
p
ut Disabled
Output Disabled
0
Output Disabled
Output Disabled
Out
p
ut Disabled
0
Down s
p
read
Down spread
See Table 2: PLL3 Quick Configuration
Only applies if Byte 0, bit 2 = 0.
DOT96
Center s
p
read
Center spread
SRC0
01
1
SATA = SRC_Main
Configuration Not Saved
iAMT Enabled
SRC Main = PLL3
See Table 1 : CPU Frequency Select Table
Legacy Mode
SRC Main = PLL1
Configuration Saved
SATA = PLL2
PCI from PLL1 PCI from SRC_MAIN
IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
21
Byte 5 Clock Request Enable/Configuration Register
Bit Pin Name Description Type Default
7 CR#_A_EN
Enable CR#_A (clk req),
PCI0_OE must be = 1 for this bit to take effect
RW 0
6 CR#_A_SEL Sets CR#_A to control either SRC0 or SRC2 RW 0
5 CR#_B_EN Enable CR#_B (clk req) RW 0
4 CR#_B_SEL Sets CR#_B -> SRC1 or SRC4 RW 0
3 CR#_C_EN Enable CR#_C (clk req) RW 0
2 CR#_C_SEL Sets CR#_C -> SRC0 or SRC2 RW 0
1 CR#_D_EN Enable CR#_D
(
clk re
q)
RW 0
0 CR#_D_SEL Sets CR#_D -> SRC1 or SRC4 RW 0
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit Pin Name Description Type Default
7 CR#_E_EN Enable CR#_E (clk req) -> SRC6 RW 0
6 CR#_F_EN Enable CR#_F (clk req) -> SRC8 RW 0
5 CR#_G_EN Enable CR#_G
(
clk re
q)
-> SRC9 RW 0
4 CR#_H_EN Enable CR#_H (clk req) -> SRC10 RW 0
3 Reserved Reserved RW 0
2 Reserved Reserved RW 0
1
SSCD_STP_CRTL
(SRC1)
If set, SSCD (SRC1) stops with PCI_STOP# RW 0
0 SRC_STP_CRTL If set, SRCs (except SRC1) stop with PCI_STOP# RW 0
Byte 7 Vendor ID/ Revision ID
Bit Pin Name Description Type Default
7 Rev Code Bit 3 R X
6 Rev Code Bit 2 R X
5 Rev Code Bit 1 R X
4 Rev Code Bit 0 R X
3 Vendor ID bit 3 R 0
2 Vendor ID bit 2 R 0
1 Vendor ID bit 1 R 0
0 Vendor ID bit 0 R 1
Byte 8 Device ID and Output Enable Register
Bit Pin Name Description Type Default
7
Device_ID3 R 0
6
Device_ID2 R 0
5
Device_ID1 R 0
4
Device_ID0 R 0
3 Reserved Reserved RW 0
2 Reserved Reserved RW 0
1 SE1_OE Output enable for SE1 RW 0
0 SE2_OE
Output enable for SE2
RW 0
Byte 9 Output Control Register
Bit Pin Name Description Type Default
7 PCIF5 STOP EN Allows control of PCIF5 with assertion of PCI_STOP# RW 0
6 TME_Readback Truested Mode Enable
(
TME
)
stra
p
status
R
0
5 Reserved Reserved RW 1
4 Test Mode Select Allows test select, ignores REF/FSC/TestSel RW 0
3 Test Mode Entry Allows entr
y
into test mode, i
g
nores FSB/TestMode RW 0
2 IO_VOUT2 IO Output Voltage Select (Most Significant Bit) RW 1
1 IO_VOUT1 IO Output Voltage Select RW 0
0 IO_VOUT0 IO Output Voltage Select (Least Significant Bit) RW 1
Disabled
Revision ID
Vendor specific
01
Vendor ID
ICS is 0001, binary
Enabled
Enabled
Normal o
p
eration
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
See Device ID Table
-
-
Disabled
-
-
Disable CR#_A
CR#_A -> SRC0
01
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
Enable CR#_A
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
0
Disable CR#_E
Disable CR#_F
Disable CR#_G
Stops with PCI_STOP#
assertion
Disable CR#_H
Free Running
Enable CR#_E
1
01
Enable CR#_H
Enable CR#_G
Enable CR#_F
Stops with PCI_STOP#
assertion
Free Running
Test mode
Free running
normal o
p
eration
Outputs HI-Z
-
Stops with PCI_STOP#
assertion
no overclockin
g
-
Outputs = REF/N
See Table 3: V_IO Selection
(Default is 0.8V)
01
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

9LPRS502SFLFT

Mfr. #:
Buy 9LPRS502SFLFT
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner PC MAIN CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet