IDT
TM
/ICS
TM
56-pin CK505 w/Fully Integrated Voltage Regulator + Integrated Series Resistor 1125E—02/26/09
Advance Information
ICS9LPRS502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR + INTEGRATED SERIES RESISTOR
25
Test Clarification Table
Comments
FSLC/
TEST_SEL
HW PIN
FSLB/
TEST_MOD
E
HW PIN
TEST
ENTRY BIT
B9b3
REF/N or
HI-Z
B9b4
OUTPUT
<2.0V X 0 0 NORMAL
>2.0V 0 X 0 HI-Z
>2.0V 0 X 1 REF/N
>2.0V 1 X 0 REF/N
>2.0V 1 X 1 REF/N
<2.0V X 1 0 HI-Z
<2.0V X 1 1 REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
HW S
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
