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NCV7708DW

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
NCV7708
http://onsemi.com
10
DETAILED OPERATING DESCRIPTION
General
The NCV7708 Double Hex Driver provides drive
capability for 3 independent H−Bridge configurations, or 6
High Side configurations with 6 Low Side configurations, or
any combination of arrangements. Each output drive is
characterized for a 500 mA load and has a typical 1.0 A surge
capability (at 12 V). Strict adherence to integrated circuit die
temperature is necessary. Maximum die temperature is
150°C. This may limit the number of drivers enabled at one
time. Output drive control and fault reporting is handled via
the SPI (Serial Peripheral Interface) port.
An Enable function (EN) provides a low quiescent sleep
current mode when the device is not being utilized. No data
is stored when the device is in sleep mode. A pull down
current source is provided on the EN input to ensure the
device is off if the input signal is lost. Pull down current
sources are also provided on the SI and SCLK inputs. A pull
up current source is provided for the CSB input for the same
reason. A loss of signal pulls the CSB input high to stop any
spurious signals into the SPI port.
Power Up/Down Control
An under voltage lockout circuit prevents the output
drivers from turning on unintentionally. This control is
provided by monitoring the voltages on the VS1, VS2, and
V
CC
pins. Each analog power pin (VS1 or VS2) powers their
respective output drivers (VS1 powers OUTH1, OUTH2,
OUTH3, all 6 charge pumps and all 6 low side pre−drivers.
VS2 powers OUTH4, OUTH5, and OUTH6). All drivers are
initialized in the off (high impedance) condition, and will
remain off regardless of the status of V
CC
. This allows
power up sequencing of V
CC
, VS1, and VS2 up to the user.
The voltage on VS1 and VS2 should be operated at the same
potential.
A built−in hysteresis on the under voltage threshold is
included to prevent an unknown region on the power pins.
After a device has powered up and the output drivers are
allowed to turn on, the output drivers will not turn off until
the voltage on the supply pins is reduced from the initial
under voltage threshold, or if shut down by either a SPI
command or a fault condition.
Internal power−up circuitry on the logic supply pin
supports a smooth turn on transition. V
CC
power up resets
the internal logic such that all output drivers will be off as
power is applied. Exceeding the under voltage lockout
threshold on V
CC
allows information to be input through the
SPI port for turn on control. Logic information remains
intact over the entire VS1 and VS2 voltage range.
Current Limitation
Input bit 13 (OCD) controls the action of driver shutoff
during current limit. With a 0 for bit 13, there is no driver
shutoff, and the drivers current limit at 3 A. With a 1 for input
bit 13, the output drivers shut off when the shutdown
threshold current is passed. Devices can be turned back on
via the SPI port. Note: high currents could cause a high rise
in die temperature. Devices will not turn on if the die
temperature exceeds the thermal shutdown temperature.
Over Current Detection Shut Down
OCD Input
Bit 13
OUTx OCD
Condition
Output Data Bit 13 Over
Load Detect (OLD) Status
OUTx Status
Current Limit
of all Drivers
0 0 0 Unchanged 3 A
0 1 1 (Need SRR to reset) Unchanged 3 A
1 0 0 Unchanged 3 A
1 1 1 (Need SRR to reset) OUTx Latches Off (Need SRR to reset) 3 A
Under load Detection
The under−load detection is accomplished by monitoring
the current from each output driver. A minimum load current
(this is the maximum open circuit detection threshold) is
required when the drivers are turned on. If the under−load
circuit detection threshold has been crossed for more than
the under−load delay time, the bit indicator (output bit #14)
for open circuit will be set to a 1. In addition, the offending
driver will be turned off only if input bit 14 (ULD) is set to
1 (true).
Under Load Detection Shut Down
ULD Input
Bit 14
OUTx ULD
Condition
Output Data Bit 14 Under
Load Detect (ULD) Status
OUTx Status
0 0 0 Unchanged
0 1 1 (Need SRR to reset) Unchanged
1 0 0 Unchanged
1 1 1 (Need SRR to reset) OUTx Latches Off (Need SRR to reset)
NCV7708
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11
Over Voltage Shutdown
Over voltage shutdown circuitry monitors the voltage on
the VS1 and VS2 pins. When the Over−voltage Threshold
voltage level has been breached on both or either one of the
VSx supply inputs, output bit 15 will be set and, if input bit
15 (OVLO) is set to 1, all outputs will turn off. Turn on/off
status is maintained in the logic circuitry. When proper input
voltage levels are re−established, the programmed outputs
will turn back on. Over−voltage shutdown can be disabled
by using the SPI input bit 15 (OVLO = 0).
Over Voltage Lock Out (OVLO) Shut Down
OVLO In-
put Bit 15
VSx OVLO
Condition
Output Data Bit 15 Power
Supply Fail (PSF) Status
OUTx Status
0 0 0 Unchanged
0 1 1 (Need SRR to reset) Unchanged
1 0 0 Unchanged
1 1 1 (Need SRR to reset) All Outputs Off (Remain off until VSx is out of OVLO)
Thermal Shutdown
Six independent thermal shutdown circuits are featured
(one common sensor for each HS and LS transistor pair).
Each sensor has two levels, one to give a Thermal Warning
(TW) and a higher one, Over Temperature, which will shut
the drivers off. When the part reaches the temperature point
of Thermal Warning, the output data bit 0 (TW) will be set
to a 1, and the outputs will remain on. With one or more
sensors detecting the over temperature level, all channels
will be turned off simultaneously. All outputs will return to
normal operation when the part thermally recovers
(Thermal toggling), because the over temperature shutdown
does not change the actual channel selection. The output
data bit 0, Thermal Warning, will latch and remain set, even
after cooling, and is reset by using a software command to
input bit 0 (SRR). Since thermal warning precedes a thermal
shutdown, software polling of this bit will allow for load
control and possible prevention of thermal shutdown
conditions.
Thermal warning information can be retrieved
immediately without performing a complete SPI access
cycle. Figure 4 below displays how this is accomplished.
Bringing the CSB pin from a 1 to a 0 condition immediately
displays the information on the output data bit 0, thermal
warning, even in the absence of a SCLK signal. As the
temperature of the NCV7708 changes from a condition from
below the thermal warning threshold to above the thermal
warning threshold, the state of the SO pin changes and this
level is available immediately when the CSB goes to 0. A 0
on SO indicates there is no thermal warning, while a 1
indicates the IC is above the thermal warning threshold. This
warning bit is reset by using the input data bit 0, SRR.
Figure 4. Access to Temperature warning information shows the thermal information is available immediately
with activation of the CSB signal without having to toggle the SCLK line.
CSB
SCLK
SO
CSB
SCLK
SO
TWH
NTW
No Thermal WarningThermal Warning High
Tristate Level
Tristate Level
NCV7708
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12
Typical Operating Characteristics
Figure 5. Typical High−side Negative Clamp
Voltage vs. Reverse Current, Room Temperature
Figure 6. V
CC
Sleep Supply Current vs.
Temperature
HIGH SIDE PIN VOLTAGE (V) T
J
, TEMPERATURE (°C)
−4.0−3.0−2.0−1.00
0
−0.2
−0.4
−0.6
−0.8
−1.0
−1.2
150100500−50
0
1.0
2.0
3.0
4.0
V
CC
SUPPLY CURRENT (mA)
HIGH SIDE CURRENT (A)
Applications Drawing
The applications drawing below displays the range with
which this part can drive a multitude of loads. The dotted line
connecting the outputs exhibits the NCV7708 diversity.
1. H−Bridge Driver configuration
2. Low Side Driver
3. High Side Driver
Figure 7. Application Drawing
M
VSx
OUTHx
OUTLx
GND
VSx
OUTHx
OUTLx
GND
21
3
+
Any combination of motors and high side drivers can be designed in. This allows for flexibility in many systems.
H−Bridge Driver Configuration
The NCV7708 has the flexibility of controlling each
driver independently. When the device is set up in an
H−Bridge configuration, the software design has to take care
of avoiding simultaneous activation of connected HS and LS
transistors. Resulting high shoot through currents could
cause irreversible damage to the device.
Overvoltage Clamping − Driving Inductive Loads
To avoid excessive voltages when driving inductive loads
in a single−side−mode (LS or HS switch, no freewheeling
path), external clamping diodes for inductive turn off of the
low side driver must be provided. The maximum clamp
voltage is 48 V. Due to high power dissipation during
clamping, the maximum energy capability of the driver
transistor has to be considered.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

NCV7708DW

Mfr. #:
Buy NCV7708DW
Manufacturer:
ON Semiconductor
Description:
Motor / Motion / Ignition Controllers & Drivers HALF BRIDGE DRIVER
Lifecycle:
New from this manufacturer.
Delivery:
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