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LTC3562EUD#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
LTC3562
10
3562fa
V
OUT
Adjustable (Type-B) Regulators
Unlike the Type-A regulators, the two Type-B regulators
do not require an external resistor divider network to
program its output voltage. Regulators R600B and R400B
have feedback resistor networks internal to the chip whose
values can be adjusted through I
2
C control. These inter-
nal feedback resistors can be confi gured such that the
output voltages can be programmed directly. The output
voltages can be programmed from 600mV to 3.775V in
25mV increments.
Pins OUT600B and OUT400B are feedback sense pins that
connect to the top of the internal resistor divider networks.
These output pins should sense the output voltages of
the regulators right at the output capacitor C
O
(after the
inductor), as illustrated in Figure 2.
The maximum operating current for regulators R600B and
R400B are 600mA and 400mA, respectively. The Type-B
regulators do not have individual run pins as do the Type-A
regulators. Thus regulators R600B and R400B can only
be enabled through control of the I
2
C port. When the
part initially powers up, the Type-B regulators default to
shutdown mode and remain disabled until programmed
through I
2
C.
Regulator Operating Modes
All of the LTC3562’s switching regulators include four
possible operating modes to meet the noise/power needs
of a variety of applications.
In pulse skip mode, an internal latch is set at the start of
every cycle which turns on the main P-channel MOSFET
switch. During each cycle, a current comparator compares
the peak inductor current to the output of an error amplifi er.
The output of the current comparator resets the internal
latch which causes the main P-channel MOSFET switch to
turn off and the N-channel MOSFET synchronous rectifi er
to turn on. The N-channel MOSFET synchronous rectifi er
turns off at the end of the 2.25MHz cycle or if the current
through the N-channel MOSFET synchronous rectifi er
drops to zero. Using this method of operation, the error
amplifi er adjusts the peak inductor current to deliver the
required output power. All necessary compensation is
internal to the switching regulator requiring only a single
ceramic output capacitor for stability. At light loads in
pulse skip mode, the inductor current may reach zero
on each pulse which will turn off the N-channel MOSFET
synchronous rectifi er. In this case, the switch node (SW)
goes high impedance and the switch node voltage will
“ring.” This is discontinuous mode operation, and is
normal behavior for a switching regulator. At very light
loads in pulse skip mode, the switching regulators will
automatically skip pulses as needed to maintain output
regulation. At high duty cycle (V
OUT
> V
IN
/2) it is possible
for the inductor current to reverse at light loads, causing
the step-down switching regulator to operate continuously.
When operating continuously, regulation and low noise
output voltage are maintained, but input operating current
will increase to a couple mA.
In forced Burst Mode operation, the switching regulators
use a constant-current algorithm to control the inductor
current. By controlling the inductor current directly and
using a hysteretic control loop, both noise and switch-
ing losses are minimized. In this mode output power is
limited. While operating in forced Burst Mode operation,
Figure 2. Type-B Regular Application Circuit
OPERATION
L
SWxB
OUTxB
600mV to 3.775V
GND
LTC3562
3562 F02
C
O
LTC3562
11
3562fa
the output capacitor is charged to a voltage slightly higher
than the regulation point. The step-down converter then
goes into sleep mode, during which the output capacitor
provides the load current. In sleep mode, most of the
regulator’s circuitry is powered down, helping conserve
battery power and increase effi ciency. When the output
voltage drops below a predetermined value, the switching
regulator circuitry is powered on and another burst cycle
begins. The duration for which the regulator operates in
sleep mode depends on the load current. The sleep time
decreases as the load current increases. Forced Burst Mode
operation has a maximum deliverable output current of
about 140mA for the 600mA regulators and 100mA for
the 400mA regulators. Beyond the maximum deliverable
output current, the step-down switching regulator will not
enter sleep mode and the output will drop out of regula-
tion. Forced Burst Mode operation provides a signifi cant
improvement in effi ciency at light loads at the expense of
higher output ripple when compared to pulse skip mode.
For many noise-sensitive systems, forced Burst Mode
operation might be undesirable at certain times (i.e.,
during a transmit or receive cycle of a wireless device),
but highly desirable at others (i.e., when the device is in
low power standby mode). The I
2
C port can be used to
enable or disable forced Burst Mode operation at any time,
offering both low noise and low power operation when
they are needed.
In Burst Mode operation, the switching regulator automati-
cally switches between fi xed frequency pulse skip operation
and hysteretic control as a function of the load current. At
light loads the regulators operate in hysteretic mode and
at heavy loads they operate in constant-frequency mode.
The constant-frequency mode provides the same output
ripple and effi ciency as pulse skip mode while hysteretic
mode provides slightly lower output ripple than forced
Burst Mode operation at the expense of slightly lower
effi ciency.
Finally, the switching regulators have an LDO mode that
gives a DC option for regulating their output voltages. In
LDO mode, the switching regulators are converted to linear
regulators and deliver continuous power from their SWx
pins through their respective inductors. This mode gives
the lowest possible output noise as well as low quiescent
current at light loads.
Dropout Operation
It is possible for V
IN
to approach a switching regulator’s
programmed output voltage (e.g., a battery voltage of 3.4V
with a programmed output voltage of 3.3V). When this
happens, the PMOS switch duty cycle increases until it is
turned on continuously at 100%. In this dropout condi-
tion, the respective output voltage equals the regulator’s
input voltage minus the voltage drops across the internal
P-channel MOSFET and the inductor.
Soft-Start Operation
Soft-start is accomplished by gradually increasing the
peak inductor current for each switching regulator over
a 500μs period. This allows each output to rise slowly,
helping minimize the battery in-rush current. A soft-
start cycle occurs whenever a given switching regula-
tor is enabled, or after a fault condition has occurred
(thermal shutdown). A soft-start cycle is not triggered
by changing operating modes. This allows seamless
output operation when transitioning between Burst
Mode operation, forced Burst Mode operation, pulse
skip mode or LDO mode.
Switching Slew Rate Control
The step-down switching regulators contain new pat-
ent pending circuitry to limit the slew rate of the switch
node (SWx). This new circuitry is designed to transition
the switch node over a period of a couple nanoseconds,
signifi cantly reducing radiated EMI and conducted supply
noise, while keeping effi ciency high.
Step-Down Switching Regulator in Shutdown
The step-down switching regulators are in shutdown when
not enabled for operation. In shutdown, all circuitry in
the step-down switching regulator is disconnected from
the switching regulator input supply, leaving only a few
nano-amps of leakage current. The step-down switch-
ing regulator outputs are individually pulled to ground
through a 2k resistor on the switch pin (SWx) when in
shutdown.
OPERATION
LTC3562
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I
2
C Interface
The LTC3562 may communicate with a host (master) using
the standard I
2
C 2-wire interface. The Timing Diagram in
Figure 4 shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus Accelerator,
are required on these lines. The LTC3562 is a receive-only
(slave) device. The I
2
C control signals, SDA and SCL are
scaled internally to the DV
CC
supply. DV
CC
should be con-
nected to the same power supply as the microcontroller
generating the I
2
C signals.
The I
2
C port has an undervoltage lockout on the DV
CC
pin. When DV
CC
is below approximately 1V, the I
2
C serial
port is cleared and the two switching Type-A regulators
are set to full scale.
Bus Speed
The I
2
C port is designed to be operated at speeds of up
to 400kHz. It has built-in timing delays to ensure correct
operation when addressed from an I
2
C compliant master
device. It also contains input fi lters designed to suppress
glitches should the bus become corrupted.
START and STOP Conditions
A bus master signals the beginning of a communication
to a slave device by transmitting a start condition. A start
condition is generated by transitioning SDA from high
to low while SCL is high. When the master has fi nished
communicating with the slave, it issues a stop condition
by transitioning SDA from low to high while SCL is high.
The bus is then free for communication with another I
2
C
device.
Byte Format
Each byte sent to the LTC3562 must be 8 bits long fol-
lowed by an extra clock cycle for the Acknowledge bit to
be returned by the LTC3562. The data should be sent to
the LTC3562 most signifi cant bit (MSB) fi rst.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave (LTC3562) lets the master know
that the latest byte of information was received. The
Acknowledge-related clock pulse is generated by the
master. The master releases the SDA line (HIGH) during
the Acknowledge clock cycle. The slave-receiver must pull
down the SDA line during the Acknowledge clock pulse
so that it remains a stable low during the high period of
this clock pulse.
Slave Address Byte
The LTC3562 responds to only one 7-bit address which
has been factory programmed to 11001010. The eighth
bit of the address byte (R/W) must be 0 for the LTC3562
to recognize the address since it is a write-only device.
This effectively forces the address to be 8 bits long where
the least signifi cant bit of the address is 0. If the correct
7-bit address is given but the R/W bit is 1, the LTC3562
will not respond.
Sub-Address Byte
The sub-address byte uses bits A7 through A4 to specify
the regulator(s) being programmed by that particular
three-byte sequence (refer to Table 2). A specifi c regulator
gets programmed if its corresponding sub-address bit is
high, whereas the regulator ignores the 3-byte sequence
if its sub-address bit is low. Note that multiple regulators
can be programmed by the same 3-byte sequence if more
than one of the sub-address bits are high. Bits A1 and A0
of the sub-address byte are used to program the operating
mode (Table 3). Bits A3 and A2 of the sub-address byte
are not used.
Data Byte
The data byte only affects the regulators that are specifi ed
to be programmed by the sub-address byte. The MSB
of the data byte (B7) is used to enable or disable the
regulator(s) being programmed. A high B7 indicates an
enable command, whereas a low B7 indicates a shutdown
command.
OPERATION
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LTC3562EUD#PBF

Mfr. #:
Buy LTC3562EUD#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Quad Synch Step-Down DC/DC Regulator
Lifecycle:
New from this manufacturer.
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