LTC3562
14
3562fa
If a Type-A regulator is being programmed, then bits B3
through B0 program the DAC that controls the regulator’s
feedback servo voltage. This 4-bit sequence programs the
feedback voltage from 425mV to 800mV in 25mV incre-
ments (Table 4). Bits B6 through B4 are not used when
programming a Type-A regulator.
If a Type-B regulator is being programmed, then bits B6
through B0 program the DAC that controls the regulator’s
output voltage. This 7-bit sequence programs the output
voltage from 600mV to 3.775V in 25mV increments
(Tables 5 and 6).
Bus Write Operation
The master initiates communication with the LTC3562 with
a start condition and a 7-bit address followed by the write
bit R/W = 0. If the address matches that of the LTC3562,
the LTC3562 returns an Acknowledge. The master should
then deliver the sub-address byte for the regulator(s)
being programmed. Again the LTC3562 acknowledges
and then the data byte is delivered starting with the most
signifi cant bit. The data byte and the two mode bits in the
sub-address byte are transferred to an internal holding
latch for each programmed regulator upon the return
of an Acknowledge. After the sub-address byte and data
byte have been transferred to the LTC3562, the master
may terminate the communication with a stop condition.
Alternatively, a repeat-start condition can be initiated by
the master and the entire sequence can be repeated, this
time accessing a different sub-address code to program
another regulator. Likewise, the master can also initiate a
Repeat-Start so that another chip on the I
2
C bus can be
addressed. This cycle can continue indefi nitely and the
LTC3562’s regulators will remember the last input of valid
data that it received. Once all chips on the bus have been
addressed and sent valid data, a global stop condition can
be sent and the LTC3562 will update its regulators with
the data that it had received.
In certain circumstances the data on the I
2
C bus may
become corrupted. In these cases the LTC3562 responds
appropriately by preserving only the last set of complete
data that it has received. For example, assume the LTC3562
has been successfully addressed and is receiving data
when a stop condition mistakenly occurs. The LTC3562
will ignore this stop condition and will not respond until a
new start condition, correct address, new set of data and
stop condition are transmitted.
Likewise, with only one exception, if the LTC3562 was
previously addressed and sent valid data but not updated
with a Stop, it will respond to any Stop that appears on
the bus, independent of the number of Repeat-Starts that
have occurred. If a Repeat-Start is given and the LTC3562
successfully acknowledges its address, it will not respond
to a Stop until all three bytes of the new data have been
received and acknowledged.
I
2
C Examples
To program R600A in forced Burst Mode operation with
its feedback servo voltage set to 600mV:
Sub-Address Byte – 1000XX10
Data Byte – 1XXX0111
To program R600B and R400B in LDO mode with their
output voltages set to 1.250V:
Sub-Address Byte – 0011XX01
Data Byte – 10011010
To put the entire chip in shutdown and disable all regula-
tors:
Sub-Address Byte – 1111XXXX
Data Byte – 0XXXXXXX
Disabling the I
2
C Port
The I
2
C serial port can be disabled by grounding the DV
CC
pin. In this mode, regulators R600A and R400A can only be
activated through the individual logic input pins RUN600A
and RUN400A. Disabling the I
2
C port also resets the feed-
back servo voltages to the default setting of 0.8V.
Note that if the I
2
C port gets disabled while a Type-A
regulator is enabled and its RUN pin is activated, the
regulator will remain enabled and its feedback voltage will
immediately be reset to the default setting of 0.8V. If the
I
2
C port gets disabled and the RUN pins are not activated,
then the regulators will immediately go into shutdown
mode. Since regulators R600B and R400B do not have
RUN pins, they immediately go into shutdown once the
I
2
C port gets disabled.
OPERATION
