© 2009 Microchip Technology Inc. DS21948E-page 15
MCP3905/06
4.0 DEVICE OVERVIEW
The MCP3905/06 is an energy-metering IC that
supplies a frequency output proportional to active (real)
power, and higher frequency output proportional to the
instantaneous power for meter calibration. Both
channels use 16-bit, second-order, delta-sigma ADCs
that oversample the input at a frequency equal to
MCLK/4, allowing for wide dynamic range input signals.
A Programmable Gain Amplifier (PGA) increases the
usable range on the current input channel (Channel 0).
The calculation of the active (real) power, as well as the
filtering associated with this calculation, is performed in
the digital domain, ensuring better stability and drift
performance. Figure 4-1 represents the simplified
block diagram of the MCP3905/06, detailing its main
signal-processing blocks.
Two digital high-pass filters cancel the system offset on
both channels such that the real-power calculation
does not include any circuit or system offset. After
being high-pass filtered, the voltage and current signals
are multiplied to give the instantaneous power signal.
This signal does not contain the DC offset components,
such that the averaging technique can be efficiently
used to give the desired active (real) power output.
The instantaneous power signal contains the real-
power information; it is the DC component of the
instantaneous power. The averaging technique can be
used with both sinusoidal and non-sinusoidal
waveforms, as well as for all power factors. The
instantaneous power is thus low-pass filtered in order
to produce the instantaneous real-power signal.
A DTF converter accumulates the instantaneous active
(real) power information to produce output pulses with a
frequency proportional to the average active (real)
power. The low-frequency pulses presented at the
F
OUT0
and F
OUT1
outputs are designed to drive
electromechanical counters and two-phase stepper
motors displaying the real-power energy consumed.
Each pulse corresponds to a fixed quantity of real
energy, selected by the F2, F1 and F0 logic settings. The
HF
OUT
output has a higher frequency setting and lower
integration period such that it can represent the
instantaneous active (real) power signal. Due to the
shorter accumulation time, it enables the user to
proceed to faster calibration under steady load
conditions (refer to Section 4.7 “F
OUT0/1
and HF
OUT
Output Frequencies”).
FIGURE 4-1: Simplified MCP3905/06 Block Diagram with Frequency Contents.
HPF
...1010..
DTF
–
+
ADC
–
+
PGA
LPF
HPF
X
CH0+
CH0-
CH1+
CH1-
ADC
F
OUT0
F
OUT1
HF
OUT
0 0
MCP3905/06
0 00
Frequency
Content
ΔΣ
ΔΣ
ADC Output
Code Contains
System and
ADC Offset
DC Offset
Removed
by HPF
Instantaneous
Power
ANALOG DIGITAL
Instantaneous
Active (Real) Power
Input Signal
with System
Offset and
Line Frequency
