MCP3905LT-I/SS Datasheet MCP3905LT-I/SS | P16-P18

MCP3905/06

4.1 Analog Inputs

The MCP3905/06 analog inputs can be connected

directly to the current and voltage transducers (such as

shunts or current transformers). Each input pin is

protected by specialized Electrostatic Discharge (ESD)

structures that are certified to pass 5 kV HBM and

500V MM contact charge. These structures also allow

up to ±6V continuous voltage to be present at their

inputs without the risk of permanent damage.

Both channels have fully differential voltage inputs for

better noise performance. The absolute voltage at each

pin relative to A

GND

should be maintained in the ±1V

range during operation in order to ensure the measure-

ment error performance. The common mode signals

should be adapted to respect both the previous

conditions and the differential input voltage range. For

best performance, the common mode signals should

be referenced to A

GND

The current channel comprises a PGA on the front-end

to allow for smaller signals to be measured without

additional signal conditioning. The maximum

differential voltage specified on Channel 0 is equal to

±470 mV/Gain (see Table 4-1). The maximum peak

voltage specified on Channel 1 is equal to ±660 mV.

4.2 16-Bit Delta-Sigma ADCs

The ADCs used in the MCP3905/06 for both current

and voltage channel measurements are delta-sigma

ADCs. They comprise a second-order, delta-sigma

modulator using a multi-bit DAC and a third-order SINC

filter. The delta-sigma architecture is very appropriate

for the applications targeted by the MCP3905, because

it is a waveform-oriented converter architecture that

can offer both high linearity and low distortion

performance throughout a wide input dynamic range. It

also creates minimal requirements for the anti-aliasing

filter design. The multi-bit architecture used in the ADC

minimizes quantization noise at the output of the

converters without disturbing the linearity.

Both ADCs have a 16-bit resolution, allowing wide input

dynamic range sensing. The oversampling ratio of both

converters is 64. Both converters are continuously

converting during normal operation. When the MCLR

pin is low, both converters will be in Reset and output

code 0x0000h. If the voltage at the inputs of the ADC is

larger than the specified range, the linearity is no longer

specified. However, the converters will continue to

produce output codes until their saturation point is

reached. The DC saturation point is around 700 mV for

Channel 0 and 1V for Channel 1, using internal voltage

reference.

The clocking signals for the ADCs are equally

distributed between the two channels in order to

minimize phase delays to less than 1 MCLK period

(see Section 3.2 “High-Pass Filter Input Logic Pin

(HPF)”). The SINC filters main notch is positioned at

MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing

the user to be able to measure wide harmonic content

on either channel. The magnitude response of the

SINC filter is shown in Figure 4-2.

FIGURE 4-2: SINC Filter Magnitude

Response (MCLK = 3.58 MHz).

4.3 Ultra-Low Drift V

REF

The MCP3905/06 contains an internal voltage

reference source specially designed to minimize drift

over temperature. This internal V

REF

supplies

reference voltage to both current and voltage channel

ADCs. The typical value of this voltage reference is

2.4V, ±100 mV. The internal reference has a very low

typical temperature coefficient of ±15 ppm/°C, allowing

the output frequencies to have minimal variation with

respect to temperature since they are proportional to

(1/V

REF

)².

REFIN/OUT is the output pin for the voltage reference.

Appropriate bypass capacitors must be connected to

the REFIN/OUT pin for proper operation (see

Section 5.0 “Applications Information”). The

voltage reference source impedance is typically 4 kΩ,

which enables this voltage reference to be overdriven

by an external voltage reference source.

TABLE 4-1: MCP3905 GAIN SELECTIONS

G1 G0 CH0 Gain

Maximum

CH0 Voltage

00 1±470mV

01 2±235mV

10 8±60mV

11 16 ±30 mV

TABLE 4-2: MCP3906 GAIN SELECTIONS

G1 G0 CH0 Gain

Maximum

CH0 Voltage

00 1±470mV

01 32 ±15 mV

10 8±60mV

11 16 ±30 mV

-120

-100

-80

-60

-40

-20

0 5 10 15 20 25 30

Frequency (kHz)

Normal Mode Rejection (dB)

MCP3905/06

If an external voltage reference source is connected to

the REFIN/OUT pin, the external voltage will be used

as the reference for both current and voltage channel

ADCs. The voltage across the source resistor will then

be the difference between the internal and external

voltage. The allowed input range for the external

voltage source goes from 2.2V to 2.6V for accurate

measurement error. A V

REF

value outside of this range

will cause additional heating and power consumption

due to the source resistor, which might affect

measurement error.

4.4 Power-On Reset (POR)

The MCP3905/06 contains an internal POR circuit that

monitors analog supply voltage AV

during operation.

This circuit ensures correct device startup at system

power-up/power-down events. The POR circuit has

built-in hysteresis and a timer to give a high degree of

immunity to potential ripple and noise on the power

supplies, allowing proper settling of the power supply

during power-up. A 0.1 µF decoupling capacitor should

be mounted as close as possible to the AV

pin,

providing additional transient immunity (see

Section 5.0 “Applications Information”).

The threshold voltage is typically set at 4V, with a

tolerance of about ±5%. If the supply voltage falls below

this threshold, the MCP3905/06 will be held in a Reset

condition (equivalent to applying logic ‘0’ on the MCLR

pin). The typical hysteresis value is approximately

200 mV in order to prevent glitches on the power

supply.

Once a power-up event has occurred, an internal timer

prevents the part from outputting any pulse for

approximately 1s (with MCLK = 3.58 MHz), thereby

preventing potential metastability due to intermittent

resets caused by an unsettled regulated power supply.

Figure 4-3 illustrates the different conditions for a

power-up and a power-down event in the typical

conditions.

FIGURE 4-3: Power-on Reset Operation.

4.5 High-Pass Filters and Multiplier

The active (real) power value is extracted from the DC

instantaneous power. Therefore, any DC offset

component present on Channel 0 and Channel 1

affects the DC component of the instantaneous power

and will cause the real-power calculation to be

erroneous. In order to remove DC offset components

from the instantaneous power signal, a high-pass filter

has been introduced on each channel. Since the

high-pass filtering introduces phase delay, identical

high-pass filters are implemented on both channels.

The filters are clocked by the same digital signal,

ensuring a phase difference between the two channels

of less than one MCLK period. Under typical conditions

(MCLK = 3.58 MHz), this phase difference is less than

0.005°, with a line frequency of 50 Hz. The cut-off

frequency of the filter (4.45 Hz) has been chosen to

induce minimal gain error at typical line frequencies,

allowing sufficient settling time for the desired

applications. The two high-pass filters can be disabled

by applying a logic ‘0’ to the HPF pin.

FIGURE 4-4: HPF Magnitude Response

(MCLK = 3.58 MHz).

The multiplier output gives the product of the two high-

pass-filtered channels, corresponding to instantaneous

active (real) power. Multiplying two sine wave signals

by the same ω frequency gives a DC component and a

2ω component. The instantaneous power signal

contains the active (real) power of its DC component,

while also containing 2ω components coming from the

line frequency multiplication. These 2ω components

come for the line frequency (and its harmonics) and

must be removed in order to extract the real-power

information. This is accomplished using the low-pass

filter and DTF converter.

4.2V

DEVICE

MODE

RESET

PROPER

OPERATION

RESET

PULSE

OUT

Time

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequency (Hz)

Normal Mode Rejection (dB)

MCP3905/06

4.6 Low-Pass Filter and DTF

Converter

The MCP3905/06 low-pass filter is a first-order IIR filter

that extracts the active (real) power information

(DC component) from the instantaneous power signal.

The magnitude response of this filter is detailed in

Figure 4-5. Due to the fact that the instantaneous power

signal has harmonic content (coming from the 2ω

components of the inputs), and since the filter is not

ideal, there will be some ripple at the output of the

low-pass filter at the harmonics of the line frequency.

The cut-off frequency of the filter (8.9 Hz) has been

chosen to have sufficient rejection for commonly-used

line frequencies (50 Hz and 60 Hz). With a standard

input clock (MCLK = 3.58 MHz) and a 50 Hz line

frequency, the rejection of the 2ω component (100 Hz)

will be more than 20 dB. This equates to a 2ω

component containing 10 times less power than the

main DC component (i.e., the average active (real)

power).

FIGURE 4-5: LPF Magnitude Response

(MCLK = 3.58 MHz).

The output of the low-pass filter is accumulated in the

DTF converter. This accumulation is compared to a

different digital threshold for F

OUT0/1

and HF

OUT

representing a quantity of real energy measured by the

part. Every time the digital threshold on F

OUT0/1

OUT

is crossed, the part will output a pulse

(See Section 4.7 “F

OUT0/1

and HF

OUT

Output

Frequencies”).

The equivalent quantity of real energy required to

output a pulse is much larger for the F

OUT0/1

outputs

than the HF

OUT

. This is such that the integration period

for the F

OUT0/1

outputs is much larger. This larger

integration period acts as another low-pass filter so that

the output ripple due to the 2ω components is minimal.

However, these components are not totally removed,

since realized low-pass filters are never ideal. This will

create a small jitter in the output frequency. Averaging

the output pulses with a counter or a Microcontroller

Unit (MCU) in the application will then remove the small

sinusoidal content of the output frequency and filter out

the remaining 2ω ripple.

OUT

is intended to be used for calibration purposes

due to its instantaneous power content. The shorter

integration period of HF

OUT

demands that the 2ω

component be given more attention. Since a sinusoidal

signal average is zero, averaging the HF

OUT

signal in

steady-state conditions will give the proper real energy

value.

-40

-35

-30

-25

-20

-15

-10

-5

0.1 1 10 100 1000

Frequency (Hz)

Normal Mode Rejection (dB)

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MCP3905LT-I/SS

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Manufacturer:

Microchip Technology

Description:

Data Acquisition ADCs/DACs - Specialized Dynamic Range Energy Meter IC

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