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XRT71D04IV

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P22
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
12
SYSTEM DESCRIPTION
The XRT71D04 is an integrated 4-channel E3/DS3/
STS-1 jitter attenuator that attenuates the jitter from
the input clock and data. The jitter attenuation perfor-
mance meets the latest specifications such as Bellcore
GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T
G.751,ITU-T G.752 and ITU-T G.755 standards.
The XRT71D04 also meets both the mapping and
pointer adjustment jitter generation criteria for both
Category I and Category II interfaces as specified in
Bellcore GR-253.
The XRT71D04 also meets the DS3 wander specifi-
cation that apply to SONET and asynchronous inter-
faces as specified in the ANSI T1.105.03b 1997 stan-
dard.
For support of loop-timing applications, the
XRT71D04 can also be used to reduce and limit the
amount of jitter in the recovered line clock signal.
Figure 5 presents a simple block diagram of the
XRT71D04, when it is configured to operate in the
Hardware Mode and Figure 6 presents a simple block
diagram of the XRT71D04, when it is configured to
operate in the Host Mode.
F
IGURE
5. A
TYPICAL
C
HANNEL
_
N
OF
THE
XRT71D04
CONFIGURED
TO
OPERATE
IN
THE
H
ARDWARE
M
ODE
FSS
HOST
Reset
DS3/E3_n
16/32 Bit FIFO
Timing Control Block /
Phase locked Loop
Write Clock Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
DJA_n
RClk_n
RCLKES
RPOS_n
RNEG_n
ICT
MCLK_n
Jittery
Clock
Smoothed
Clock
RRCLKES
XRT71D04
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4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
13
The XRT71D04 DS3/E3 Jitter Attenuator IC consists
of the following functional blocks:
•
The Jitter-Attenuator PLL
•
Timing Control Block
•
The 2-Channel 16/32 Bit FIFO
•
Serial Microprocessor Interface
1.0 JITTER ATTENUATOR PLL
1.1 B
ACKGROUND
I
NFORMATION
1.1.1 Definition of Jitter
One of the most important and least understood mea-
sures of clock performance is jitter. The International
Telecommunication Union defines jitter as short term
variations of the significant instants of a digita signal
from their ideal positions in time. Jitter can occur due
to any of the following:
1) Imperfect timing recovery circuit in the system
2) Cross-talk noise
3) Inter-symbol interference/Signal Distortion
1.1.2 SONET STS-1 to DS3 Mapping
SONET equipment jitter criteria are specified as:
i) Jitter Transfer
ii) Jitter Tolerance
iii) Jitter Generation
1.2 J
ITTER
T
RANSFER
C
HARACTERISTICS
The primary purpose of jitter transfer requirements is
to prevent performance degradations by limiting the
accummulation of jitter through the system such that
it does not exceed the network interface jitter require-
ments. Thus, it is more important that a system meet
the jitter transfer criteria for relatively high input jitter
amplitudes. The jitter transferred through the system
must be under the jitter mask for any input jitter ampli-
tude within the range as shown in Figure 7
F
IGURE
6. A
TYPICAL
C
HANNEL
_
N
OF
THE
XRT71D04
CONFIGURED
TO
OPERATE
IN
THE
H
OST
M
ODE
HOST
Reset
16/32 Bit FIFO
Microprocessor Serial
Interface
Timing Control Block /
Phase locked Loop
Write Clock Read Clock
RRCLK_n
RRPOS_n
RRNEG_n
FL_n
RCLK_n
RPOS_n
RNEG_n
ICT
CS SDI SDO SClk
MClkn
Smoothed
Clock
Jittery
Clock
RRCLKES
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XRT71D04
4 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR, STS-1 TO DS3 DESYNCHRONIZER
REV. 1.1.1
14
1.2.1 Jitter Tolerance
The jitter tolerance in the network element is defined
as the maximum amount of jitter in the incoming sig-
nal that it can receive in an error-free manner.
1.2.2 Jitter Generation
Jitter generation is defined in Section 7.3.3 of GR-
499-CORE. Jitter generation criteria exists for both
Category I and II interfaces, which consist of mapping
and pointer adjustment jitter generation.
Mapping jitter is the sum of the intrinsic payload map-
ping jitter and the jitter that is generated as a result of
the bit stuffing mechnisms used in all of the asynchro-
nous DSn mapping into STS SPE.
1.2.3 Jitter Attenuation
A digital Jitter Attenuation loop combined with the
FIFO provides Jitter attenuation. The Jitter Attenuator
requires no external components except for the refer-
ence clock.
Data is clocked into the FIFO with the associated
clock signal (TClk or RClk) and clocked out of the
FIFO with the dejittered clock and data. When the
FIFO is within 2 bits of being completely full, the FIFO
Limit (FL) will be set.
In Figure 5and Figure 6, this de-jittered clock is la-
beled Smoothed Clock. This Smoothed Clock is now
used to Read Out the Recovered Data from the 16/32
bit FIFO. This Smoothed Clock will also be output to
the Terminal Equipment via the RRClk output pin.
Likewise, the Smoothed Recovered Data will output
to the Terminal Equipment via the RRPOS and
RRNEG output pins.
The XRT71D04 is designed to work as a companion
device with XRT73L04 (STS-1/DS3/E3) Line Inter-
face Unit.
ETSI TBR24 specifies the maximum output jitter in
loop timing must be no more than 0.4UIpp when mea-
sured between 100Hz to 800KHzwith upto 1.5UI input
jitter at 100Hz. This means a jitter attenuator with
bandwidth less than 100Hz is required to be compli-
ant with the standard. ITU G.751 is another applica-
tion where low bandwidth jitter attenuator is needed
to smooth the gapped clock output in the de-multi-
plexer system.
1.2.4 SONET STS-1 DS3 Mapping
Bellcore GR-253 section 3.4.2 and the ANSI T1.105-
199 describes the asynchronous mapping for DS3 in-
to STS-1 SPE.
F
IGURE
7. C
ATEGORY
1 DS3 J
ITTER
T
RANSFER
M
ASK
0.1
Jitter Gain
(dB)
Acceptable
Range
40
Frequency (Hz)
slope = -20 dB/decade
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XRT71D04IV

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Buy XRT71D04IV
Manufacturer:
MaxLinear
Description:
Clock Synthesizer / Jitter Cleaner 4CH E3/DS3/STS1 JIT ATTEN DE-SYNCH
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New from this manufacturer.
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