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M1026-13-155.5200

P1-P3P4-P6P7-P9P10-P12P13-P14
M1025/26 Datasheet Rev 1.0 Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1025/26
VCSO BASED CLOCK PLL WITH AUTOSWITCH
Integrated
Circuit
Systems, Inc.
Product Data Sheet
GENERAL DESCRIPTION
The M1025/26 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for optical network systems
supporting up to 2.5Gb data rates.
It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1025/26 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
FEATURES
◆ Integrated SAW delay line; low phase jitter of < 0.5ps
rms, typical (12kHz to 20MHz)
◆ Output frequencies of 62.5 to 175 MHz
(Specify VCSO output frequency at time of order)
◆ LVPECL clock output (CML and LVDS options available)
◆ Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
◆ Loss of Lock (LOL) output pin; Narrow Bandwidth
control input (NBW pin)
◆ AutoSwitch (AUTO pin) - automatic (non-revertive)
reference clock reselection upon clock failure
◆ Acknowledge pin (REF_ACK pin) indicates the actively
selected reference input
◆ Hitless Switching (HS) options with or without Phase
Build-out (PBO) to enable SONET (GR-253) /SDH
(G.813) MTIE and TDEV compliance during reselection
◆ Pin-selectable feedback and reference divider ratios
◆ Single 3.3V power supply
◆ Small 9 x 9 mm SMT (surface mount) package
PIN ASSIGNMENT (9 x 9 mm SMT)
Figure 1: Pin Assignment
SIMPLIFIED BLOCK DIAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using
M1025-11-155.5200 or M1026-11-155.5200
Input Reference
Clock (MHz)
PLL Ratio
(Pin Selectable)
Output Clock
(MHz)
(Pin Selectable)
(M1025) (M1026)
19.44 or 38.88
(M1025) (M1026)
8 or 4
155.52
or
77.76
77.76 2
155.52 1
622.08 0.25
Table 1: Example I/O Clock Frequency Combinations
M1025
M1026
(Top View)
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
MR_SEL3
GND
NC
DIF_REF0
nDIF_REF0
REF_SEL
DIF_REF1
nDIF_REF1
VCC
P_SEL0
P_SEL1
nFOUT
FOUT
GND
REF_ACK
AUTO
VCC
GND
MR_SEL2
MR_SEL0
MR_SEL1
LOL
NBW
VCC
DNC
DNC
DNC
nOP_IN
OP_OUT
VC
nVC
nOP_OUT
OP_IN
GND
GND
GND
19
20
21
22
23
24
25
26
27
FOUT
nFOUT
TriState
Loop Filter
PLL
Phase
Detector
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
P_SEL1:0
NBW
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL
Phase
Detector
REF_ACK
AUTO
M1025/26
VCSO
P Divider
LUT
LOL
2
M Divider
4
M/R Divider
LUT
MR_SEL3:0
P Divider
(1, 2, or TriState)
M1025/26 VCSO Based Clock PLL with AutoSwitch
M1025/26 Datasheet Rev 1.0 2 of 14 Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
PIN DESCRIPTIONS
Number Name I/O Configuration Description
1, 2, 3, 10, 14, 26 GND
Ground Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 5, External Loop Filter, on pg. 9.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 19, 33 VCC
Power Power supply connection, connect to +3.3V.
12 AUTO
Input Internal pull-down resistor
1
Automatic/manual reselection mode for clock input:
Logic
1 automatic reselection upon clock failure
(non-revertive)
Logic
0 manual selection only (using REF_SEL)
13 REF_ACK
Output
Reference Acknowledgement pin for input mux state; outputs
the currently selected reference input pair:
Logic
1 indicates nDIF_REF1, DIF_REF1
Logic 0 indicates nDIF_REF0, DIF_REF0
15
16
FOUT
nFOUT
Output No internal terminator Clock output pair. Differential LVPECL (CML, LVDS available).
17
18
P_SEL1
P_SEL0
Internal pull-down resistor
1
Note 1: For typical values of internal pull-down and pull-UP resistors, see DC Characteristics on pg. 11.
Post-PLL , P divider selection. LVCMOS/LVTTL. See Table 5,
P Divider Look-Up Table (LUT),
on pg. 4.
20 nDIF_REF1
Input
Biased to Vcc/2
2
Note 2: Biased toVcc/2, with 50kΩ
to Vcc and 50kΩ to ground. See Differential Inputs Biased to VCC/2 on pg. 11.
Reference clock input pair 1. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
21 DIF_REF1
Internal pull-down resistor
1
22 REF_SEL
Input Internal pull-down resistor
1
Referenc
e clock input selection.
LVCMOS/LVTTL:
Logic
1 selects DIF_REF1, nDIF_REF1.
Logic 0 selects DIF_REF0, nDIF_REF0.
23 nDIF_REF0
Input
Biased to Vcc/2
2
Reference clock input pair 0. Differential LVPECL or LVDS.
Resistor bias on inverting terminal supports TTL or LVCMOS.
24 DIF_REF0
Internal pull-down resistor
1
25 NC
No internal connection.
27
28
29
30
MR_SEL3
MR_SEL2
MR_SEL0
MR_SEL1
Input Internal pull-down resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See Tables 3 and 4, M and R Divider Look-Up Tables (LUT)
on pg. 3.
31 LOL
Output
Loss of Lock indicator output. Asserted when internal PLL is
not tracking the input reference for frequency and phase.
3
Logic 1 indicates loss of lock.
Logic
0 indicates locked condition.
Note 3: See LVC M O S O ut p u t in DC Characteristics on pg. 11.
32 NBW
Input Internal pull-UP resistor
1
Narrow Bandwidth enable. LVCMOS/LVTTL:
Logic
1 - Narrow loop bandwidth, R
IN
= 2100kΩ.
Logic
0 - Wide bandwidth, R
IN
= 100kΩ.
34, 35, 36 DNC
Do Not Connect.
Table 2: Pin Descriptions
M1025/26 Datasheet Rev 1.0 3 of 14 Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
Integrated
Circuit
Systems, Inc.
DETAILED BLOCK DIAGRAM
Figure 3: Detailed Block Diagram
DIVIDER SELECTION TABLES
M and R Divider Look-Up Tables (LUT)
The
MR_SEL3:0 pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance. The look-up tables vary
by device variant. M1025 and M1026 are defined in
Ta bl es
3
and
4 respectively
.
M1025 M/R Divider LUT
ables 3 and
4
provide example Fin and phase
detector frequencies with 155.52MHz VCSO
devices (M1025-11-155.5200
and M1026-11-155.5200).
See “Ordering Information” on pg. 14.
M1026 M/R Divider LUT
Phase
Locked
Loop
(PLL)
M1025/26
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VCnVC
R
POST
nOP_OUTOP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN nOP_IN
PLL
Phase
Detector
Loop Filter
Am plifier
External
Loop Filter
Components
MR_SEL3:0
R Div
MUX
0
REF_SEL
DIF_REF0
nDIF_REF0
1
M Divider
NBW
R
IN
R
IN
M / R Divider
LUT
DIF_REF1
nDIF_REF1
Auto
Ref Sel
0
1
LOL
Phase
Detector
REF_ACK
AUTO
LOL
FOUT
nFOUT
P_SEL1:0
P Divider
LUT
P Divider
(1, 2, or TriState)
4
2
TriState
Hitless Switching (HS) Opt.
HS with Phase Build-out Opt.
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0 8 1 8 19.44 19.44
0 0 0 1 32 4 8 19.44 4.86
0 0 1 0 128 16 8 19.44 1.215
0 0 1 1 512 64 8 19.44 0.30375
0 1 0 0 2 1 2 77.76 77.76
0 1 0 1 8 4 2 77.76 19.44
0 1 1 0 32 16 2 77.76 4.86
0 1 1 1 128 64 2 77.76 1.215
1 0 0 0 1 1 1 155.52 155.52
1 0 0 1 4 4 1 155.52 38.88
1 0 1 0 16 16 1 155.52 9.72
1 0 1 1 64 64 1 155.52 2.43
1 1 0 0 Test Mode
1
Note 1: Factory test mode; do not use.
N/A N/A N/A
1 1 0 1 1 4 0.25 622.08 155.52
1 1 1 0 4 16 0.25 622.08 38.88
1 1 1 1 16 64 0.25 622.08 9.72
Table 3: M1025 M/R Divider LUT
MR_SEL3:0
M Div R Div
Total
PLL
Ratio
Fin for
155.52MHz
VCSO (MHz)
Phase Det.
Freq. for
155.52MHz
VCSO (MHz)
0 0 0 0 4 1 4 38.88 38.88
0 0 0 1 16 4 4 38.88 9.72
0 0 1 0 64 16 4 38.88 2.43
0 0 1 1 256 64 4 38.88 0.6075
0 1 0 0 2 1 2 77.76 77.76
0 1 0 1 8 4 2 77.76 19.44
0 1 1 0 32 16 2 77.76 4.86
0 1 1 1 128 64 2 77.76 1.215
1 0 0 0 1 1 1 155.52 155.52
1 0 0 1 4 4 1 155.52 38.88
1 0 1 0 16 16 1 155.52 9.72
1 0 1 1 64 64 1 155.52 2.43
1 1 0 0 Test Mode
1
Note 1: Factory test mode; do not use.
N/A N/A N/A
1 1 0 1 1 4 0.25 622.08 155.52
1 1 1 0 4 16 0.25 622.08 38.88
1 1 1 1 16 64 0.25 622.08 9.72
Table 4: M1026 M/R Divider LUT
P1-P3P4-P6P7-P9P10-P12P13-P14

M1026-13-155.5200

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IC PLL JITTER ATTENUATOR 36CLCC
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