M1025/26 Datasheet Rev 1.0 8 of 14 Revised 28Jul2004
Integrated Circuit Systems, Inc. ● Networking & Communications ● www.icst.com ● tel (508) 852-5400
Integrated
Circuit
Systems, Inc.
M1025/26
VCSO B
ASED
C
LOCK
PLL
WITH
A
UTO
S
WITCH
Product Data Sheet
Optional Hitless Switching and Phase Build-out
The M1025/26 is available with a Hitless Switching
feature that is enabled during device manufacturing.
In addition, a Phase Build-out feature is also offered.
These features are offered as device options and are
specified by device order code. Refer to “Ordering
Information” on pg. 14.
The Hitless Switching feature (with or without Phase
Build-out) is designed for applications where switching
occurs between two stable system reference clocks. It
should not be used in loop timing applications, or when
reference clock jitter is greater than 1 ns pk-pk. Hitless
Switching is triggered by the LOL circuit, which is
activated by a 4 ns phase transient. This magnitude of
phase transient can generated by the CDR (Clock &
Data Recovery unit) in loop timing mode, especially
during a system jitter tolerance test. It can also be
generated by some types of Stratum clock DPLLs
(digital PLL), especially those that do not include a post
de-jitter APLL (analog PLL).
When the Hitless Switching feature is enabled, it is
always triggered by LOL, whether in AutoSwitch mode
(
AUTO pin high) or Select mode (AUTO pin low). For
example, in Manual mode, the Hitless Switching feature
operates when LOL goes high even if there is no
reselection of the input mux. This enables the use of an
upstream clock mux (such as on the host card), while
still providing MTIE compliance when readjusting to the
resultant phase change.
When the M1025/26 is operating in wide bandwidth
mode (
NBW=0), the optional Hitless Switching function
puts the device into narrow bandwidth mode when
activated. This allows the PLL to lock the new input
clock phase gradually. With proper configuration of the
external loop filter, the output clock complies with MTIE
and TDEV specifications for GR-253 (SONET) and ITU
G.813 (SDH) during input reference clock changes.
The optional proprietary Phase Build-out (PBO)
function enables the PLL to absorb most of the phase
change of the input clock. The PBO function selects a
new VCSO clock edge for the PLL Phase Detector
feedback clock, selecting the edge closest in phase to
the new input clock phase. This reduces re-lock time,
the generation of wander, and extra output clock cycles.
The Hitless Switching and Phase Build-out functions
are triggered by the LOL circuit. For proper operation,
a low phase detector frequency must be avoided. See
“Guidelines Using LOL” on pg. 6 for information
regarding the phase detector frequency.
HS/PBO Triggers
The HS function (or the combined HS/PBO function)
is armed after the device locks to the input clock refer-
ence. Once armed, HS is triggered by the occurance of
a Loss of Lock condition. This would typically occur as a
consequence of a clock reference failure, a clock failure
upstream to the M1025/26, or a M1025/26 clock refer-
ence mux reselection.
When pin AUTO = 1 (automatic reference
reselection mode) HS is used in conjunction with
input reselection. When AUTO = 0 (manual mode),
HS will still occur upon an input phase transient,
however the clock input is not reselected (this
enables hitless switching when using an external
MUX for clock selection).
HS/PBO Operation
Once triggered, the following HS/PBO sequence
occurs:
1. The HS function disables the PLL Phase Detector
and puts the device into NBW (narrow bandwidth)
mode. The internal resistor Rin is changed to
2100kΩ
. See the Narrow Bandwidth (NBW) Control
Pin on pg. 8.
2. If included, the PBO function adds to (builds out) the
phase in the clock feedback path (in VCSO clock
cycle increments) to align the feedback clock with
the (new) reference clock input phase.
3. The PLL Phase Detector is enabled, allowing the
PLL to re-lock.
4. Once the PLL Phase Detector feedback and input
clocks are locked to within 2 ns for eight consecutive
cycles, a timer (WBW timer) for resuming wide
bandwidth (in 175 ns) is started.
5. When the WBW timer times out, the device reverts
to wide loop bandwidth mode (i.e., Rin is returned to
100kΩ) and the HS/PBO function is re-armed.
Narrow Bandwidth (NBW) Control Pin
A Narrow Loop Bandwidth control pin (
NBW pin) is
included to adjust the PLL loop bandwidth. In wide
bandwidth mode (
NBW=0), the internal resistor Rin is
100kΩ
. With the NBW pin asserted, the internal resistor
Rin is changed to 2100kΩ
. This lowers the loop
bandwidth by a factor of about 21 (approximately 2100 /
100) and lowers the damping factor by a factor of about
4.6 (the square root of 21), assuming the same loop
filter components.
