XRA1206
11
REV. 1.0.0 8-BIT I2C/SMBUS GPIO EXPANDER WITH INTEGRATED LEVEL SHIFTERS
5. For IRQ# signal;
Test 1: SCL frequency is 400 KHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
Test 2: SCL frequency is 400 KHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level
should be the same as VCC. All GPIOs are configured as inputs. SCL and SDA are at VCC. Outputs are left floating or in
tri-state mode.
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40
o
to +85
o
C, Vcc=1.65V - 3.6V
SYMBOL PARAMETER
STANDARD MODE
C-BUS
MIN MAX
FAST MODE
C-BUS
MIN MAX
UNIT
f
SCL
Operating frequency 0 100 0 400 kHz
T
BUF
Bus free time between STOP and START 4.7 1.3 µs
T
HD;STA
START condition hold time 4.0 0.6 µs
T
SU;STA
START condition setup time 4.7 0.6 µs
T
HD;DAT
Data hold time 0 0 ns
T
VD;ACK
Data valid acknowledge 0.6 0.6 µs
T
VD;DAT
SCL LOW to data out valid 0.6 0.6 ns
T
SU;DAT
Data setup time 250 150 ns
T
LOW
Clock LOW period 4.7 1.3 µs
T
HIGH
Clock HIGH period 4.0 0.6 µs
T
F
Clock/data fall time 300 300 ns
T
R
Clock/data rise time 1000 300 ns
T
SP
Pulse width of spikes tolerance 50 50 ns
T
D1
I
2
C-bus GPIO output valid
0.2 0.2 µs
T
D4
I
2
C input pin interrupt valid
4 4 µs
T
D5
I
2
C input pin interrupt clear
4 4 µs
T
D15
SCL delay after reset 3 3 µs
I
2
I
2
