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IS61C5128AL-10TLI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
Integrated Silicon Solution, Inc. — www.issi.com7
Rev. C1
12/18/2016
IS61C5128AL/AS IS64C5128AL/AS
READ CYCLE SwITCHING CHARACTERISTICS
(1)
(OverOperatingRange)
-10 -12 -25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
trC ReadCycleTime 10 — 12 — 25 — ns
taa AddressAccessTime — 10 — 12 — 25 ns
toha OutputHoldTime 3 — 3 — 3 — ns
taCe CEAccessTime — 10 — 12 — 25 ns
tdoe OEAccessTime — 5 — 6 — 15 ns
thzoe
(2)
OEtoHigh-ZOutput 0 5 0 6 0 8 ns
tlzoe
(2)
OEtoLow-ZOutput 0 — 0 — 2 — ns
thzCe
(2)
CEtoHigh-ZOutput 0 5 0 6 0 8 ns
tlzCe
(2)
CEtoLow-ZOutput 2 — 2 — 2 — ns
AC TEST CONDITIONS
Parameter Unit
InputPulseLevel 0Vto3.0V
InputRiseandFallTimes 3ns
InputandOutputTiming 1.5V
andReferenceLevel
OutputLoad SeeFigures1and2
480 Ω
30 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
480 Ω
5 pF
Including
jig and
scope
255 Ω
OUTPUT
5V
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to
3.0VandoutputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. Not100%tested.
Figure1
Figure2
AC TEST LOADS
8 Integrated Silicon Solution, Inc. — www.issi.com
Rev. C1
12/18/2016
IS61C5128AL/AS IS64C5128AL/AS
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t
AA
t
OHA
t
OHA
t
RC
DOUT
ADDRESS
t
RC
t
OHA
t
AA
t
DOE
t
LZOE
t
ACS
t
LZCS
t
HZOE
HIGH-Z
DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t
HZCS
Notes:
1. WEisHIGHforaReadCycle.
2. Thedeviceiscontinuouslyselected.OE, CE =
Vil.
3. AddressisvalidpriortoorcoincidentwithCELOWtransitions.
READ CYCLE NO. 2
(1,3)
AC wAVEFORMS
READ CYCLE NO. 1
(1,2)
Integrated Silicon Solution, Inc. — www.issi.com 9
Rev. C1
12/18/2016
IS61C5128AL/AS IS64C5128AL/AS
wRITE CYCLE SwITCHING CHARACTERISTICS
(1,3)
(OverOperatingRange)
-10 -12 -25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
twC WriteCycleTime 10 — 12 — 25 — ns
tsCe CEtoWriteEnd 7 — 9 — 18 — ns
taw AddressSetupTime 7 — 9 — 18 — ns
toWriteEnd
tha AddressHoldfromWriteEnd 0 — 0 — 0 — ns
tsa AddressSetupTime 0 — 0 — 0 — ns
tPwe1 WEPulseWidth(OE=High) 7 — 9 — 15 — ns
tPwe2 WEPulseWidth(OE=Low) 7 — 9 — 15 — ns
tsd DataSetuptoWriteEnd 6 — 6 — 15 — ns
thd DataHoldfromWriteEnd 0 — 0 — 0 — ns
thzwe
(2)
WELOWtoHigh-ZOutput — 6 — 6 — 15 ns
tlzwe
(2)
WEHIGHtoLow-ZOutput 3 — 3 — 5 — ns
Notes:
1. Testconditionsassumesignaltransitiontimesof3nsorless,timingreferencelevelsof1.5V,inputpulselevelsof0to3.0Vand
outputloadingspeciedinFigure1.
2. TestedwiththeloadinFigure2.Transitionismeasured±500mVfromsteady-statevoltage.Not100%tested.
3. TheinternalwritetimeisdenedbytheoverlapofCELOW,andWELOW.AllsignalsmustbeinvalidstatestoinitiateaWrite,
butanyonecangoinactivetoterminatetheWrite.TheDataInputSetupandHoldtimingarereferencedtotherisingorfalling
edge of the signal that terminates the write.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

IS61C5128AL-10TLI

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Buy IS61C5128AL-10TLI
Manufacturer:
ISSI
Description:
SRAM 4M (512Kx8) 10ns Async SRAM
Lifecycle:
New from this manufacturer.
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