December 1990 18
Philips Semiconductors Product specification
9-bit x 64-word FIFO register; 3-state 74HC/HCT7030
Expanded format
Fig.19 shows two cascaded FIFOs providing a capacity of 128 words × 9 bits.
Fig.20 shows the signals on the nodes of both FIFOs after the application of a SI pulse, when both FIFOs are initially
empty. After a rippled through delay, data arrives at the output of FIFO
A
. Due to SO
A
being HIGH, a DOR pulse is
generated. The requirements of SI
B
and D
nB
are satisfied by the DOR
A
pulse width and the timing between the rising
edge of DOR
A
and Q
nA
. After a second ripple through delay, data arrives at the output of FIFO
B
.
Fig.21 shows the signals on the nodes of both FIFOs after the application of a SO
B
pulse, when both FIFOs are initially
full. After a bubble-up delay a DIR
B
pulse is generated, which acts as a SO
A
pulse for FIFO
A
. One word is transferred
from the output of FIFO
A
to the input of FIFO
B
. The requirements of the SO
A
pulse for FIFO
A
is satisfied by the pulse
width of DOR
B
. After a second bubble-up delay an empty space arrives at D
nA
, at which time DIR
A
goes HIGH.
Fig.22 shows the waveforms at all external nodes of both FIFOs during a complete shift-in and shift-out sequence.
Fig.19 Cascading for increased word capacity; 128 words × 9 bits.
The PC74HC/HCT7030 is easily cascaded to increase word capacity without any
external circuitry. In cascaded format, all necessary communications are handled
by the FIFOs. Figs 17 to 19 demonstrate the intercommunication timing between
FIFO
A
and FIFO
B
. Fig.22 gives an overview of pulses and timing of two cascaded
FIFOs, when shifted full and shifted empty again.
