673M-01LFT Datasheet 673M-01LFT, 673M-01ILF, 673M-01LF | P4-P6

PLL BUILDING BLOCK

MDS 673-01 L 4 Revision 051310

www.idt.com

ICS673-01

AC Electrical Characteristics

VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C, C

LOAD

at CLK = 15 pF, unless stated otherwise

VDD = 5.0V ±10%, Ambient Temperature -40 to +85° C, C

LOAD

at CLK = 15 pF, unless stated otherwise

Note 1: Minimum input frequency is limited by loop filter design. 1 kHz is a practical minimum limit.

External Components

The ICS673-01 requires a minimum number of external

components for proper operation. A decoupling

capacitor of 0.01μF should be connected between VDD

and GND as close to the ICS673-01 as possible. A

series termination resistor of 33 Ω may be used at the

clock output.

Special considerations must be made in choosing loop

components C

and C

. These can be found online at

http://www.idt.com

Avoiding PLL Lockup

In some applications, the ICS673-01 can “lock up” at

the maximum VCO frequency. This is usually caused

by power supply glitches or a very slow power supply

ramp. This situation also occurs if the external divider

starts to fail at high input frequencies. The usual failure

mode of a divider circuit is that the output of the divider

begins to miss clock edges. The phase detector

interprets this as a too low output frequency and

Parameter Symbol Conditions Min. Typ. Max. Units

Output Clock Frequency

(from pin CLK)

CLK

SEL = 1 1 100 MHz

SEL = 0 0.25 25 MHz

Input Clock Frequency

(into pins REFIN or FBIN)

REF

Note 1 8 MHz

Output Rise Time t

0.8 to 2.0V 1.2 2 ns

Output Fall Time t

2.0 to 0.8V 0.75 1.5 ns

Output Clock Duty Cycle t

At VDD/2 40 50 60 %

Jitter, Absolute peak-to-peak t

250 ps

VCO Gain K

190 MHz/V

Charge Pump Current I

2.5 μA

Parameter Symbol Conditions Min. Typ. Max. Units

Output Clock Frequency

(from pin CLK)

CLK

SEL = 1 1 120 MHz

SEL = 0 0.25 30 MHz

Input Clock Frequency

(into pins REFIN or FBIN)

REF

Note 1 8 MHz

Output Rise Time t

0.8 to 2.0V 0.5 1 ns

Output Fall Time t

2.0 to 0.8V 0.5 1 ns

Output Clock Duty Cycle t

At VDD/2 45 50 55 %

Jitter, Absolute peak-to-peak t

150 ps

VCO Gain K

190 MHz/V

Charge Pump Current I

2.4 μA

PLL BUILDING BLOCK

MDS 673-01 L 5 Revision 051310

www.idt.com

ICS673-01

increases the VCO frequency. The feedback divider

begins to miss even more clock edges and the VCO

frequency is continually increased until it is running at

its maximum frequency. Whether caused by power

supply issues or by the external divider, the loop can

only recover by powering down the circuit or asserting

PD.

The simplest way to avoid this problem is to use an

external divider that always operates correctly

regardless of the VCO speed. Figures 2 and 3 show

that the VCO is capable of high speeds. By using the

internal divide-by-four and/or the CLK2 output, the

maximum VCO frequency can be divided by 2, 4, or 8

and a slower counter can be used. Using the ICS673

internal dividers in this manner does reduce the

number of frequencies that can be exactly synthesized

by forcing the total VCO divide to change in increments

of 2, 4, or 8.

If this lockup problem occurs, there are several

solutions; three of which are described below.

1. If the system has a reset or power good signal, this

should be applied to the PD pin, forcing the chip to stay

powered down until the power supply voltage has

stabilized

2. If no power good signal is available, a simple

power-on reset circuit can be attached to the PD pin, as

shown in Figure 1. When the power supply ramps up,

this circuit holds PD asserted (device powered down)

until the capacitor charges.

The circuit of Figure 1A is adequate in most cases, but

the discharge rate of capacitor C3 when VDD goes low

is limited by R1. As this discharge rate determines the

minimum reset time, the circuit of Figure 1B may be

used when a faster reset time is desired. The values of

R1 and C3 should be selected to ensure that PD stays

below 1.0 V until the power supply is stable.

3. A comparator circuit may be used to monitor the loop

filter voltage as shown in Figure 2. This circuit will dump

the charge off the loop filter by asserting PD if the VCO

begins to run too fast and the PLL can recover. A good

choice for the comparator is the National

Semiconductor LMC7211BIM5X. It is low power,

version of the small (SOT-23), low cost, and has high

input impedance.

The trigger voltage of the comparator is set by the

voltage divider formed by R2 and R3. The voltage

should be set to a value higher than the VCO input is

expected to run during normal operation. Typically, this

A. Basic Circuit

ICS673-01

VDD

B. Faster Discharge

ICS673-01

VDD

Fig 1. Power on Reset Circuits

PLL BUILDING BLOCK

MDS 673-01 L 6 Revision 051310

www.idt.com

ICS673-01

might be 0.5 V below VDD. Hysteresis should be added

to the circuit by connecting R4.

The CLK output frequency may be up to 2x the

maximum Output Clock Frequency listed in the AC

Electrical Characteristics above when the device is in

an unlocked condition. Make sure that the external

divider can operate up to this frequency.

Explanation of Operation

The ICS673-01 is a PLL building block circuit that

includes an integrated VCO with a wide operating

range. The device uses external PLL loop filter

components which through proper configuration allow

for low input clock reference frequencies, such as a

15.7 kHz Hsync input.

The phase/frequency detector compares the falling

edges of the clocks inputted to FBIN and REFIN. It then

generates an error signal to the charge pump, which

produces a charge proportional to this error. The

external loop filter integrates this charge, producing a

voltage that then controls the frequency of the VCO.

This process continues until the edges of FBIN are

aligned with the edges of the REFIN clock, at which

point the output frequency will be locked to the input

frequency.

Figure 3. Example Configuration -- Generating a 20 MHz clock from a 200 kHz reference.

Figure 2. Using an External Comparator

to Reset the VCO

CHGP VCOIN

CAP

ICS673-01

REFIN

+3.3 or 5 V

SEL

VDD

0.01μF

FBIN

200 kHz

100

Digital Divider

such as ICS674-01

GND

CLK2

CAP

20 MHz

VCOIN

200 kHz

40 MHz

CLK1

P1-P3 P4-P6 P7-P8

673M-01LFT

Mfr. #:

Buy 673M-01LFT

Manufacturer:

IDT

Description:

Phase Locked Loops - PLL PLL BUILDING BLOCK

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673M-01LFT

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