673M-01LFT

PLL BUILDING BLOCK
MDS 673-01 L 7 Revision 051310
www.idt.com
ICS673-01
Determining the Loop Filter Values
The loop filter components consist of C
S
, C
P
, and R
S
.
Calculating these values is best illustrated by an
example. Using the example in Figure 1, we can
synthesize 20 MHz from a 200 kHz input.
The phase locked loop may be approximately
described by the following equations:
Bandwidth
Damping factor,
where:
K
O
= VCO gain (Hz/V)
I
cp
= Charge pump current (A)
N = Total feedback divide from VCO,
including the internal VCO post divider
C
S
= Loop filter capacitor (Farads)
R
S
= Loop filter resistor (Ohms)
As a general rule, the bandwidth should be at least 20
times less than the reference frequency, i.e.,
In this example, using the above equation, bandwidth
should be less than or equal to 10 kHz. By setting the
bandwith to 10kHz and using the first equation, R
S
can
be determined since all other variables are known. In
the example of Figure 1, N = 200, comprising the divide
by 2 on the chip (VCO post divider) and the external
divide by 100. Therefore, the bandwidth equation
becomes:
and R
S
= 26 kΩ
Choosing a damping factor of 0.7 (a minimal damping
factor than can be used to ensure fast lock time),
damping factor equation becomes:
and C
S
= 1.32 nF (1.2 nF is the nearest standard
value).
The capacitor C
P
is used to damp transients from the
charge pump and should be approximately 1/20th the
size of C
S
, i.e.,
Therefore, C
P
= 60 pF (56 pF nearest standard value).
To summarize, the loop filter components are:
C
S
= 1.2 nf
C
P
= 56 pf
R
S
= 26 kΩ
When choosing either CLK1 or CLK2 to drive the
feedback divider, IDT recommends that CLK2 be used
so that the rising edges of CLK1, CLK2, and REFIN are
all synchronized. If CLK1 is used to feedback, CLK2
may be either a rising or falling edge when compared to
CLK1 and REFIN.
NBW
R
S
K
O
I
CP
⋅⋅
2
πN
--------------------------------=
BW REFIN()20
0,000
R
S
190 10
6
2.5 10
⋅⋅
2π 200
--------------------------------------------------------------------=
0.7
25 000,
2
----------------
190 10
6
2.5 10
6
C
S
⋅⋅
200
--------------------------------------------------------------------------=
C
P
C
S
20
PLL BUILDING BLOCK
MDS 673-01 L 8 Revision 051310
www.idt.com
ICS673-01
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Ordering Information
“LF” denotes Pb free packaging, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
Part / Order Number Marking Shipping packaging Package Temperature
673M-01ILF 673M-01IL Tubes 16 pin SOIC -40 to +85° C
673M-01ILFT 673M-01IL Tape and Reel 16 pin SOIC -40 to +85° C
673M-01LF 673M-01LF Tubes 16 pin SOIC 0 to +70° C
673M-01LFT 673M-01LF Tape and Reel 16 pin SOIC 0 to +70° C
INDEX
AREA
1 2
16
D
E
SEATING
PLANE
A1
A
e
- C -
B
.10 (.004)
C
C
L
H
h x 45
Millimeters Inches
Symbol Min Max Min Max
A 1.35 1.75 .0532 .0688
A1 0.10 0.25 .0040 .0098
B 0.330.51.013.020
C 0.19 0.25 .0075 .0098
D 9.80 10.00 .3859 .3937
E 3.80 4.00 .1497 .1574
e 1.27 BASIC 0.050 BASIC
H 5.80 6.20 .2284 .2440
h 0.250.50.010.020
L 0.401.27.016.050
α 0° 8° 0° 8°

673M-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Phase Locked Loops - PLL PLL BUILDING BLOCK
Lifecycle:
New from this manufacturer.
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