selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 10 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1245 at clock rates exceeding 1.5MHz, provid-
ed that the minimum acquisition time, t
ACQ
, is kept
above 2.0µs.
Data Framing
The falling edge of CS does not start a conversion on
the MAX1245. The first logic high clocked into DIN is
interpreted as a start bit and defines the first bit of the
control byte. A conversion starts on the falling edge of
SCLK, after the eighth bit of the control byte (the PD0
bit) is clocked into DIN. The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, then the next high bit clocked into DIN is recog-
nized as a start bit; the current conversion is terminated,
and a new one is started.
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 13
SSTRB
CS
SCLK
DIN
DOUT
14 8
12
18
20
24
START
SEL2 SEL1 SEL0
UNI/
BIP
SGL/
DIF
PD1 PD0
B11
MSB
B10 B9 B2 B1
B0
LSB
FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = OPEN)
2 3 5 6 7 9 10 11 19 21 22 23
t
CONV
ACQUISITION
(SCLK = 1.5MHz)
IDLE
A/D STATE
2.0µs
PD0 CLOCK IN
t
SSTRB
t
CSH
t
CONV
t
SCK
SSTRB • • •
SCLK • • •
DOUT • • •
t
CSS
t
DO
NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.
CS • • •
Figure 9. Internal Clock Mode Timing
Figure 10. Internal Clock Mode SSTRB Detailed Timing
The fastest the MAX1245 can run is 15 clocks per conver-
sion with CS held low between conversions. Figure 11a
shows the serial-interface timing necessary to perform a
conversion every 15 SCLK cycles in external clock mode.
If CS is low and SCLK is continuous, guarantee a start bit
by first clocking in 16 zeros.
Most microcontrollers require that conversions occur in
multiples of eight SCLK clocks; 16 clocks per conversion
will typically be the fastest that a microcontroller can
drive the MAX1245. Figure 11b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1245 in internal clock mode, ready to convert with
SSTRB = high. After the power supplies have stabi-
lized, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. SSTRB is
high on power-up and, if CS is low, the first logical 1 on
DIN will be interpreted as a start bit. Until a conversion
takes place, DOUT shifts out zeros.
Power-Down
The MAX1245’s automatic power-down mode can save
considerable power when operating at speeds below
the maximum sampling rate. Figure 13 shows the aver-
age supply current as a function of the sampling rate.
You can save power by placing the converter in a low-
current shutdown state between conversions.
Select power-down via bits 1 and 0 of the DIN control
byte with SHDN high (Tables 1 and 4). Pull SHDN low at
any time to shut down the converter completely. SHDN
overrides bits 1 and 0 of the control byte (Table 5).
Power-down mode turns off all chip functions that draw
quiescent current, reducing I
DD
typically to 1.2µA.
Figures 12a and 12b illustrate the various power-down
sequences in both external and internal clock modes.
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 4, PD1 and PD0
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
14 ______________________________________________________________________________________
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0
CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONTROL BYTE 2S
1
8181
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0
CONTROL BYTE 1S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B11 B10 B9 B8
CONVERSION RESULT 1
• • •
• • •
• • •
• • •
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
MAX1245
+2.375V, Low-Power, 8-Channel,
Serial 12-Bit ADC
______________________________________________________________________________________ 15
POWERED UP
HARDWARE
POWER-
DOWN
POWERED UP
POWERED UP
12 DATA BITS
12 DATA BITS
INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
SX
XXXX
11 S 00
XXXXX XX XXX
S11
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN
SETS EXTERNAL
CLOCK MODE
SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
SOFTWARE
POWER-DOWN
POWERED UP
POWERED UP
DATA VALID
DATA VALID
INTERNAL
SX
XXXX
10 S 00
XXXXX
S
MODE
DOUT
DIN
CLOCK
MODE
SETS INTERNAL
CLOCK MODE
SETS
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 12a. Timing Diagram Power-Down Modes, External Clock
Figure 12b. Timing Diagram Power-Down Modes, Internal Clock
PD1 PD0 DEVICE MODE
1 1 External Clock
1 0 Internal Clock
0 1 Unassigned
0 0 Power-Down
SSHHDDNN
DEVICE INTERNAL CLOCK
STATE MODE FREQUENCY
1 Enabled 225kHz
Open Enabled 1.5MHz
0 Power-Down N/A
Table 4. Software Power-Down and
Clock Mode
Table 5. Hard-Wired Power-Down and
Internal Clock Frequency

MAX1245BEAP+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 10-Bit 8Ch 100ksps 3.3V Precision ADC
Lifecycle:
New from this manufacturer.
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