24
LTC1709-8/LTC1709-9
APPLICATIO S I FOR ATIO
WUU
U
Using Figure 4, the RMS ripple current will be:
I
INRMS
= (20A)(0.23) = 4.6A
RMS
An input capacitor(s) with a 4.6A
RMS
ripple current rating
is required.
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
and multiplying by the factor obtained from Figure␣ 3
along with the calculated duty factor. The output ripple in
con
tinuous mode will be highest at the maximum input
voltage since the duty factor is <50%. The maximum
output current ripple is:
∆
∆
I
V
fL
at DF
I
V
kHz H
A
VmAmV
COUT
OUT
COUTMAX
RMS
OUTRIPPLE RMS RMS
=
()
=
()
µ
()
=
=Ω
()
=
03 33
18
300 1 5
03
12
20 1 2 24
.%
.
.
.
.
.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1709. These items are also illustrated graphically in
the layout diagram of Figure␣ 10. Check the following in
your layout:
1) Are the signal and power grounds segregated? The
LTC1709 signal ground pin should return to the (–) plate
of C
OUT
separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of C
IN
, which should have
as short lead lengths as possible.
2) Does the LTC1709 V
OS
+
pin connect to the point of
load? Does the LTC1709 V
OS
–
pin connect to the load
return?
3) Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitors between
SENSE
+
and SENSE
–
pin pairs should be as close as
possible to the LTC1709. Ensure accurate current sensing
with Kelvin connections at the current sense resistor.
4) Does the (+) plate of C
IN
connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
current path formed by the input capacitor, top and bottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
5) Is the INTV
CC
1µF ceramic decoupling capacitor con-
nected closely between
INTV
CC
and the power ground pin?
This capacitor carries the MOSFET driver peak currents. A
small value is recommended to allow placement immedi-
ately adjacent to the IC.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1709.
7) Use a low impedance source such as a logic gate to drive
the PLLIN pin and keep the lead as short as possible.
The diagram in Figure 10 illustrates all branch currents in
a 2-phase switching regulator. It becomes very clear after
studying the current waveforms why it is critical to keep
the high-switching-current paths to a small physical size.
High electric and magnetic fields will radiate from these
“loops” just as radio stations transmit signals. The output
capacitor ground should return to the negative terminal of
the input capacitor and not share a common ground path
with any switched current paths. The left half of the circuit
gives rise to the “noise” generated by a switching regula-
tor. The ground terminations of the sychronous MOSFETs
and Schottky diodes should return to the negative plate(s)
of the input capacitor(s) with a short isolated PC trace
since very high switched currents are present. A separate
isolated path from the negative plate(s) of the input
capacitor(s) should be used to tie in the IC power ground
pin (PGND) and the signal ground pin (SGND). This
technique keeps inherent signals generated by high cur-
rent pulses from taking alternate current paths that have
finite impedances during the total period of the switching
regulator. External OPTI-LOOP compensation allows over-
compensation for PC layouts which are not optimized but
this is not the recommended design procedure.
