ICM7555_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 3 August 2009 4 of 22
NXP Semiconductors
ICM7555
General purpose CMOS timer
8. Limiting values
[1] Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than V
DD
+ 0.3 V or less than GND − 0.3 V may cause destructive latch-up. For this reason it is recommended that no inputs from
external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple
systems, the supply of the ICM7555 must be turned on first.
[2] Above 25 °C, derate at the following rates:
DIP8 package at 9.3 mW / °C
SO8 package at 6.2 mW / °C
[3] Refer to Section 11.2 “Power supply considerations” section.
9. Characteristics
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage 18 V
V
I
input voltage TRIGGER
[1]
−0.3 V
DD
+ 0.3 V
CONTROL_VOLTAGE −0.3 V
DD
+ 0.3 V
THRESHOLD −0.3 V
DD
+ 0.3 V
RESET −0.3 V
DD
+ 0.3 V
I
O
output current - 100 mA
P power dissipation T
amb
=25°C (still air)
[2][3]
DIP8 package - 1160 mW
SO8 package - 780 mW
T
stg
storage temperature −65 +150 °C
T
sp
solder point temperature soldering 60 s - 300 °C
Table 5. Characteristics
T
amb
=25
°
C unless otherwise specified.
Sym
bol
Parameter Conditions Min Typ Max Unit
V
DD
supply voltage T
min
≤ T
amb
≤ T
max
3 - 16 V
I
DD
supply current
[1]
V
DD
=V
min
- 50 200 µA
V
DD
=V
max
- 180 300 µA
Astable mode timing
[2][3]
∆f/f frequency stability - 1.0 5.0 %
∆f/∆V frequency variation with voltage - 0.1 3.0 %/V
∆f/∆T frequency variation with
temperature
[4]
V
DD
= 5 V - 50 - ppm/°C
V
DD
= 10 V - 75 - ppm/°C
V
DD
= 15 V - 100 - ppm/°C
V
I
input voltage TRIGGER: V
DD
= 5 V 0.29V
DD
0.31V
DD
0.34V
DD
V
CONTROL_VOLTAGE: V
DD
= 5 V 0.62V
DD
0.65V
DD
0.67V
DD
V
THRESHOLD: V
DD
= 5 V 0.63V
DD
0.65V
DD
0.67V
DD
V
RESET: V
DD
=V
min
and V
max
0.4V
DD
0.7V
DD
1.0V
DD
V
