PDF: 09005aef837d3ecf/Source: 09005aef837d3e17 Micron Technology, Inc., reserves the right to change products or specifications without notice.
JTF8C128_256x64AZ.fm - Rev. A 1/09 EN
10 ©2007 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x64, SR): 240-Pin DDR3 SDRAM UDIMM
Serial Presence-Detect
Serial Presence-Detect
Notes: 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
Serial Presence-Detect Data
For the latest serial presence-detect data, refer to Micron’s SPD page:
www.micron.com/SPD.
Table 12: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to Vss
Parameter/Condition Symbol Min Max Units
Supply voltage
Vddspd 3.0 3.6 V
Input high voltage: Logic 1; All inputs
Vih Vddspd × 0.7 Vddspd + 0.5 V
Input low voltage: Logic 0; All inputs
Vil –0.6 Vddspd × 0.3 V
Output low voltage: Iout = 3mA
Vol – 0.4 V
Input leakage current: Vin = GND to Vdd
Ili 0.10 3 µA
Output leakage current: Vout = GND to Vdd
Ilo 0.05 3 µA
Standby current
Isb 1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz
Iccr 0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz
Iccw 2 3 mA
Table 13: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to Vss
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 – µs
Data-out hold time
t
DH 200 – ns
SDA and SCL fall time
t
F – 300 ns 2
Data-in hold time
t
HD:DAT 0 – µs
Start condition hold time
t
HD:STA 0.6 – µs
Clock HIGH period
t
HIGH 0.6 – µs
Noise suppression time constant at SCL, SDA inputs
t
I–50ns
Clock LOW period
t
LOW 1.3 – µs
SDA and SCL rise time
t
R–0.3µs2
SCL clock frequency
f
SCL – 400 kHz
Data-in setup time
t
SU:DAT 100 – ns
Start condition setup time
t
SU:STA 0.6 – µs 3
Stop condition setup time
t
SU:STO 0.6 – µs
WRITE cycle time
t
WRC – 10 ms 4
