LT3724
13
3724fd
APPLICATIONS INFORMATION
For maximum efficiency, minimize R
DS(ON)
and C
RSS
.
Low R
DS(ON)
minimizes conduction losses while low C
RSS
minimizes transition losses. The problem is that R
DS(ON)
is
inversely related to C
RSS
. Balancing the transition losses
with the conduction losses is a good idea in sizing the
MOSFET. Select the MOSFET to balance the two losses.
Calculate the maximum conduction losses of the MOSFET:
P
COND
=(I
OUT(MAX)
)
2
V
OUT
V
IN
(R
DS(ON)
)
Note that R
DS(ON)
has a large positive temperature depen-
dence. The MOSFET manufacturers data sheet contains a
curve, R
DS(ON)
vs Temperature.
Calculate the maximum transition losses:
P
TRAN
= (k)(V
IN
)
2
(I
OUT(MAX)
)(C
RSS
)(f
SW
)
where k is a constant inversely related to the gate driver
current, approximated by k = 2 for LT3724 applications.
The total maximum power dissipation of the MOSFET is
the sum of these two loss terms:
P
FET(TOTAL)
= P
COND
+ P
TRAN
To achieve high supply efficiency, keep the P
FET(TOTAL)
to
less than 3% of the total output power. Also, complete
a thermal analysis to ensure that the MOSFET junction
temperature is not exceeded.
T
J
= T
A
+ P
FET(TOTAL)
θ
JA
where θ
JA
is the package thermal resistance and T
A
is the
ambient temperature. Keep the calculated T
J
below the
maximum specified junction temperature, typically 150°C.
Note that when V
IN
is high, the transition losses may
dominate. A MOSFET with higher R
DS(ON)
and lower C
RSS
may provide higher efficiency. MOSFETs with higher volt-
age V
DSS
specification usually have higher R
DS(ON)
and
lower C
RSS
.
Choose the MOSFET V
DSS
specification to exceed the
maximum voltage across the drain to the source of the
MOSFET, which is V
IN(MAX)
plus any additional ringing
on the switch node. Ringing on the switch node can be
greatly reduced with good PCB layout and, if necessary,
an RC snubber.
The internal V
CC
regulator operating range limits the maxi-
mum total MOSFET gate charge, Q
G
, to 90nC. The Q
G
vs
V
GS
specification is typically provided in the MOSFET data
sheet. Use Q
G
at V
GS
of 8V. If V
CC
is back driven from an
external supply, the MOSFET drive current is not sourced
from the internal regulator of the LT3724 and the Q
G
of the
MOSFET is not limited by the IC. However, note that the
MOSFET drive current is supplied by the internal regulator
when the external supply back driving V
CC
is not available
such as during startup or short-circuit.
The manufacturers maximum continuous drain current
specification should exceed the peak switch current,
I
OUT(MAX)
+ ∆I
L
/2.
During the supply startup, the gate drive levels are set by
the V
CC
voltage regulator, which is approximately 8V. Once
the supply is up and running, the V
CC
can be back driven
by an auxiliary supply such as V
OUT
. It is important not to
exceed the manufacturers maximum V
GS
specification.
A standard level threshold MOSFET typically has a V
GS
maximum of 20V.
Step-Down Converter: Rectifier Selection
The rectifier diode (D1 on the Functional Diagram) in a
buck converter generates a current path for the inductor
current when the main power switch is turned off. The
rectifier is selected based upon the forward voltage, re-
verse voltage and maximum current. A Schottky diode is
recommended. Its low forward voltage yields the lowest
power loss and highest efficiency. The maximum reverse
voltage that the diode will see is V
IN(MAX)
.
In continuous mode operation, the average diode cur-
rent is calculated at maximum output load current and
maximum V
IN
:
I
DIODE(AVG)
=I
OUT(MAX)
V
IN(MAX)
V
OUT
V
IN(MAX)
To improve efficiency and to provide adequate margin for
short-circuit operation, a diode rated at 1.5 to 2 times the
maximum average diode current, I
DIODE(AVG)
, is recom-
mended.
LT3724
14
3724fd
APPLICATIONS INFORMATION
Step-Down Converter: Input Capacitor Selection
A local input bypass capacitor is required for buck convert-
ers because the input current is pulsed with fast rise and
fall times. The input capacitor selection criteria are based
on the bulk capacitance and RMS current capability. The
bulk capacitance will determine the supply input ripple
voltage. The RMS current capability is used to keep from
overheating the capacitor.
The bulk capacitance is calculated based on maximum
input ripple, ∆V
IN
:
C
IN(BULK)
=
I
OUT(MAX)
V
OUT
V
IN
f
SW
V
IN(MIN)
V
IN
is typically chosen at a level acceptable to the user.
100mV-200mV is a good starting point. Aluminum elec-
trolytic capacitors are a good choice for high voltage, bulk
capacitance due to their high capacitance per unit area.
The capacitors RMS current is:
I
CIN(RMS)
= I
OUT
V
OUT
(V
IN
V
OUT
)
(V
IN
)
2
If applicable, calculate it at the worst case condition,
V
IN
= 2V
OUT
. The RMS current rating of the capacitor
is specified by the manufacturer and should exceed the
calculated I
CIN(RMS)
. Due to their low ESR (Equivalent
Series Resistance), ceramic capacitors are a good choice
for high voltage, high RMS current handling. Note that the
ripple current ratings from aluminum electrolytic capacitor
manufacturers are based on 2000 hours of life. This makes
it advisable to further derate the capacitor or to choose a
capacitor rated at a higher temperature than required.
The combination of aluminum electrolytic capacitors and
ceramic capacitors is an economical approach to meet-
ing the input capacitor requirements. The capacitor volt-
age rating must be rated greater than V
IN(MAX)
. Multiple
capacitors may also be paralleled to meet size or height
requirements in the design. Locate the capacitor very close
to the MOSFET switch and use short, wide PCB traces to
minimize parasitic inductance.
Step-Down Converter: Output Capacitor Selection
The output capacitance, C
OUT
, selection is based on the
design’s output voltage ripple, V
OUT
, and transient load
requirements. V
OUT
is a function of ∆I
L
and the C
OUT
ESR. It is calculated by:
V
OUT
= I
L
ESR +
1
(8 f
SW
C
OUT
)
The maximum ESR required to meet a V
OUT
design
requirement can be calculated by:
ESR(MAX)=
(
V
OUT
)(L)(f
SW
)
V
OUT
1–
V
OUT
V
IN(MAX)
Worst-case V
OUT
occurs at highest input voltage. Use
paralleled multiple capacitors to meet the ESR require-
ments. Increasing the inductance is an option to lower the
ESR requirements. For extremely low V
OUT
, an additional
LC filter stage can be added to the output of the supply.
Application Note 44 has some good tips on sizing an ad-
ditional output filter.
Output Voltage Programming
A resistive divider sets the DC output voltage according
to the following formula:
R2=R1
V
OUT
1.231V
1
The external resistor divider is connected to the output
of the converter as shown in Figure 2. Tolerance of the
feedback resistors will add additional error to the output
voltage.
Example: V
OUT
= 12V; R1 = 10kΩ
R2=10k
12V
1.231V
1
= 87.48k use 86.6k1%
LT3724
15
3724fd
APPLICATIONS INFORMATION
The V
FB
pin input bias current is typically 25nA, so use
of extremely high value feedback resistors could cause a
converter output that is slightly higher than expected. Bias
current error at the output can be estimated as:
V
OUT(BIAS)
= 25nA • R2
Supply UVLO and Shutdown
The SHDN pin has a precision voltage threshold with
hysteresis which can be used as an undervoltage lockout
threshold (UVLO) for the power supply. Undervoltage
lockout keeps the LT3724 in shutdown until the supply
input voltage is above a certain voltage programmed by
the user. The hysteresis voltage prevents noise from falsely
tripping UVLO.
Resistors are chosen by first selecting RB. Then:
RA = RB
V
SUPPLY(ON)
1.35V
1
V
SUPPLY(ON)
is the input voltage at which the undervoltage
lockout is disabled and the supply turns on.
Example: Select RB = 49.9kΩ, V
SUPPLY(ON)
= 14.5V (based
on a 15V minimum input voltage)
RA = 49.9kΩ
14.5V
1.35V
1
= 486.1kΩ (499kΩ resistor is selected)
If low supply current in standby mode is required, select
a higher value of RB.
The supply turn off voltage is 9% below turn on. In the
example the V
SUPPLY(OFF)
would be 13.2V.
If additional hysteresis is desired for the enable function,
an external positive feedback resistor can be used from
the LT3724 regulator output.
The shutdown function can be disabled by connecting the
SHDN pin to the V
IN
through a large value pull-up resistor.
This pin contains a low impedance clamp at 6V, so the SHDN
pin will sink current from the pull-up resistor(R
PU
):
I
SHDN
=
V
IN
6V
R
PU
Because this arrangement will clamp the SHDN pin to the
6V, it will violate the 5V absolute maximum voltage rating of
the pin. This is permitted, however, as long as the absolute
maximum input current rating of 1mA is not exceeded.
Input SHDN pin currents of <100µA are recommended: a
1MΩ or greater pull-up resistor is typically used for this
configuration.
Soft-Start
The soft-start function forces the programmed slew rate
while the converter output rises to 95% of regulation,
which corresponds to 1.185V on the V
FB
pin. Once 95%
regulation is achieved, the soft-start circuit is disabled.
The soft-start circuit will re-enable when the V
FB
pin drops
below 70% of regulation, which corresponds to 300mV
of control hysteresis on the V
FB
pin. This allows for a
controlled recovery from a “brown-out” condition.
Figure 2. Output Voltage Feedback Divider Figure 3. Undervoltage Lockout Circuit
L1
V
FB
PIN
R2
R1
V
OUT
C
OUT
3724 F02
SHDN PIN
RA
RB
V
SUPPLY
3724 F03
Figure 4.Soft-Start Circuit
R
SS
LT3724
V
OUT
C
SS1
C
SS
3724 F04
A

LT3724IFE#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators High Voltage Non-Synch Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union