Low Skew, 1-to-9, Differential-to-
HSTL Fanout Buffer
8521 DATA SHEET
4 REVISION E 6/21/16
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDO
Output Supply Voltage 1.6 1.8 2.0 V
I
DD
Power Supply Current 60 80 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
CLK_EN, CLK_SEL 2 V
DD
+ 0.3 V
V
IL
CLK_EN, CLK_SEL -0.3 0.8 V
I
IH
Input High Current
CLK_EN V
IN
= V
DD
= 3.465V 5 µA
CLK_SEL V
IN
= V
DD
= 3.465V 150 µA
I
IL
Input Low Current
CLK_EN V
IN
= 0V, V
DD
= 3.465V -150 µA
CLK_SEL V
IN
= 0V, V
DD
= 3.465V -5 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
CLK V
IN
= V
DD
= 3.465V 150 µA
nCLK V
IN
= V
DD
= 3.465V 5 µA
I
IL
Input Low Current
CLK V
IN
= 0V, V
DD
= 3.465V -5 µA
nCLK V
IN
= 0V, V
DD
= 3.465V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.15 1.3 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
0.5 V
DD
- 0.85 V
NOTE 1: For single ended applications, the maximum input voltage for CLK and nCLK is V
DD
+ 0.3V.
NOTE 2: Common mode voltage is defi ned as V
IH
.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only.
Functional operation of product at these conditions or any
conditions beyond those listed in the DC Characteristics
or AC Characteristics is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
product reliability.
REVISION E 6/21/16
8521 DATA SHEET
5 Low Skew, 1-to-9, Differential-to-
HSTL Fanout Buffer
TABLE 4D. LVPECL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current
PCLK V
DD
= V
IN
= 3.465V 150 µA
nPCLK V
DD
= V
IN
= 3.465V 5 µA
I
IL
Input Low Current
PCLK V
DD
= 3.465V, V
IN
= 0V -5 µA
nPCLK V
DD
= 3.465V, V
IN
= 0V -150 µA
V
PP
Peak-to-Peak Input Voltage 0.3 1 V
V
CMR
Common Mode Input Voltage;
NOTE 1, 2
1.5 V
DD
V
NOTE 1: Common mode voltage is defi ned as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V
DD
+ 0.3V.
TABLE 4E. HSTL DC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE
1
1.0 1.4 V
V
OL
Output Low Voltage; NOTE
1
0 0.4 V
V
OX
Output Crossover Voltage 40% x (V
OH
- V
OL
) + V
OL
60% x (V
OH
- V
OL
) + V
OL
V
V
SWING
Peak-to-Peak
Output Voltage Swing
0.6 1.1 V
NOTE 1: Outputs terminated with 50Ω to ground.
TABLE 5. AC CHARACTERISTICS, V
DD
= 3.3V±5%, V
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 500 MHz
t
PD
Propagation Delay; NOTE 1 ƒ 250MHz 1 1.8 ns
tsk(o) Output Skew; NOTE 2, 4 50 ps
tsk(pp) Part-to-Part Skew; NOTE 3, 4 250 ps
t
R
Output Rise Time 20% to 80% @ 50MHz 300 700 ps
t
F
Output Fall Time 20% to 80% @ 50MHz 300 700 ps
odc Output Duty Cycle 48 52 %
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
Measured from V
DD
/2 to the output differential crossing point for single ended input levels.
NOTE 2: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defi ned as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defi ned in accordance with JEDEC Standard 65.
Low Skew, 1-to-9, Differential-to-
HSTL Fanout Buffer
8521 DATA SHEET
6 REVISION E 6/21/16
PARAMETER MEASUREMENT INFORMATION
PART-TO-PART SKEW
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
odc & t
PERIOD

8521BYLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Drivers & Distribution 9 HSTL OUT BUFFER
Lifecycle:
New from this manufacturer.
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